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umtrx: removed unused stuff

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This commit is contained in:
Josh Blum
2014-04-18 13:51:28 -07:00
parent 54030551e3
commit 0a52a45e1b
2 changed files with 3 additions and 38 deletions
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27
fpga/top/UmTRX/u2plus_core.v
View File

@@ -26,7 +26,6 @@ module u2plus_core
input fe_clk,
input wb_clk,
input clk_icap, //ICAP timing fixes for UmTRX Spartan-6 FPGA.
output clock_ready,
input clk_to_mac,
input pps_in,
@@ -83,12 +82,6 @@ module u2plus_core
input sda_pad_i,
output sda_pad_o,
output sda_pad_oen_o,
// Clock Gen Control
output [1:0] clk_en,
output [1:0] clk_sel,
input clk_func, // FIXME is an input to control the 9510
input clk_status,
// Generic SPI
output sclk,
@@ -112,11 +105,7 @@ module u2plus_core
output aux_sen1,
output aux_sen2,
input aux_ld1,
input aux_ld2,
// GPIO to DBoards
inout [15:0] io_tx,
inout [15:0] io_rx,
input aux_ld2,
`ifndef NO_EXT_FIFO
// External RAM
@@ -436,17 +425,6 @@ module u2plus_core
assign s3_dat_i[31:8] = 24'd0;
assign s9_dat_i[31:8] = 24'd0;
// /////////////////////////////////////////////////////////////////////////
// GPIOs
wire [31:0] gpio_readback;
gpio_atr #(.BASE(SR_GPIO), .WIDTH(32))
gpio_atr(.clk(dsp_clk),.reset(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
.rx(run_rx0 | run_rx1), .tx(run_tx0 | run_tx1),
.gpio({io_tx,io_rx}), .gpio_readback(gpio_readback) );
// /////////////////////////////////////////////////////////////////////////
// Buffer Pool Status -- Slave #5
@@ -460,7 +438,7 @@ module u2plus_core
.word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0),
.word04(32'b0),.word05(32'b0),.word06({adc0_a, 4'b0, adc0_b, 4'b0}),.word07({adc1_a, 4'b0, adc1_b, 4'b0}),
.word08(status),.word09(gpio_readback),.word10(vita_time[63:32]),
.word08(status),.word09(32'b0),.word10(vita_time[63:32]),
.word11(vita_time[31:0]),.word12(compat_num),.word13({16'b0, aux_ld2, aux_ld1, button, 1'b0, clk_status, 1'b0, 10'b0}),
.word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0])
);
@@ -506,7 +484,6 @@ module u2plus_core
// Output control lines
wire [7:0] clock_outs;
assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0];
assign lms_res = clock_outs[6:5];
wire phy_reset;

14
fpga/top/UmTRX/u2plus_umtrx_v2.v
View File

@@ -128,7 +128,7 @@ module u2plus_umtrx_v2
wire CLK_TO_MAC_int, CLK_TO_MAC_int2;
// FPGA-specific pins connections
wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clk_icap, lms_clk, clock_ready;
wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clk_icap, lms_clk;
wire DivSw1, DivSw2;
OBUF DIVSW1_P_pin (.I(DivSw1),.O(DivSw1_P));
@@ -136,11 +136,6 @@ wire DivSw1, DivSw2;
OBUF DIVSW2_P_pin (.I(DivSw2),.O(DivSw2_P));
OBUF DIVSW2_N_pin (.I(~DivSw2),.O(DivSw2_N));
reg [5:0] clock_ready_d;
always @(posedge clk_fpga)
clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready};
wire dcm_rst = ~&clock_ready_d & |clock_ready_d;
//register iogress for all adc/dac signals to force IOB
reg RX1IQSEL_reg, RX2IQSEL_reg,TX1IQSEL_reg, TX2IQSEL_reg;
reg [11:0] RX1D_reg, RX2D_reg, TX1D_reg, TX2D_reg;
@@ -313,7 +308,6 @@ wire DivSw1, DivSw2;
.fe_clk (clk_icap), //1/2 dsp rate
.wb_clk (wb_clk),
.clk_icap (clk_icap),
.clock_ready (clock_ready),
.clk_to_mac (CLK_TO_MAC_int2),
.pps_in (pps),
.leds (leds_int),
@@ -353,10 +347,6 @@ wire DivSw1, DivSw2;
.sda_pad_i (sda_pad_i),
.sda_pad_o (sda_pad_o),
.sda_pad_oen_o (sda_pad_oen_o),
.clk_en (),
.clk_sel (),
.clk_func (),
.clk_status (),
.aux_scl_pad_i (aux_scl_pad_i),
.aux_scl_pad_o (aux_scl_pad_o),
.aux_scl_pad_oen_o (aux_scl_pad_oen_o),
@@ -373,8 +363,6 @@ wire DivSw1, DivSw2;
.sen_dac (SEN_DAC),
.sen_lms1 (SEN1),
.sen_lms2 (SEN2),
.io_tx (),
.io_rx (),
//Diversity switches
.DivSw1(DivSw1),
.DivSw2(DivSw2),