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umtrx: update cross clock fifo wrapper

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This commit is contained in:
Josh Blum
2014-04-16 17:43:09 -07:00
parent a207b56ca0
commit 20ea5936cb
3 changed files with 24 additions and 27 deletions
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44
fpga/fifo/fifo_2clock.v
View File

@@ -1,5 +1,5 @@
//
// Copyright 2011 Ettus Research LLC
// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
@@ -31,42 +31,44 @@ module fifo_2clock
assign src_rdy_o = ~empty;
assign write = src_rdy_i & dst_rdy_o;
assign read = src_rdy_o & dst_rdy_i;
wire dummy;
generate
if(WIDTH==36)
if((WIDTH <= 36) && (WIDTH > 19)) begin
wire [35:0] data_in_wide, data_out_wide;
assign data_in_wide[WIDTH-1:0] = datain;
assign dataout = data_out_wide[WIDTH-1:0];
if(SIZE==9)
fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk
(.rst(arst),
.wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
.rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
.wr_clk(wclk),.din(data_in_wide),.full(full),.wr_en(write),.wr_data_count(level_wclk),
.rd_clk(rclk),.dout(data_out_wide),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
else if(SIZE==11)
fifo_xlnx_2Kx36_2clk fifo_xlnx_2Kx36_2clk
(.rst(arst),
.wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
.rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
.wr_clk(wclk),.din(data_in_wide),.full(full),.wr_en(write),.wr_data_count(level_wclk),
.rd_clk(rclk),.dout(data_out_wide),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
else if(SIZE==6)
fifo_xlnx_64x36_2clk fifo_xlnx_64x36_2clk
(.rst(arst),
.wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
.rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
.wr_clk(wclk),.din(data_in_wide),.full(full),.wr_en(write),.wr_data_count(level_wclk),
.rd_clk(rclk),.dout(data_out_wide),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
else
fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk
(.rst(arst),
.wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
.rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
else if((WIDTH==19) & (SIZE==4))
.wr_clk(wclk),.din(data_in_wide),.full(full),.wr_en(write),.wr_data_count(level_wclk),
.rd_clk(rclk),.dout(data_out_wide),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
end
else if((WIDTH <= 19) && (SIZE <= 4)) begin
wire [18:0] data_in_wide, data_out_wide;
assign data_in_wide[WIDTH-1:0] = datain;
assign dataout = data_out_wide[WIDTH-1:0];
fifo_xlnx_16x19_2clk fifo_xlnx_16x19_2clk
(.rst(arst),
.wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
.rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
else if((WIDTH==18) & (SIZE==4))
fifo_xlnx_16x19_2clk fifo_xlnx_16x19_2clk
(.rst(arst),
.wr_clk(wclk),.din({1'b0,datain}),.full(full),.wr_en(write),.wr_data_count(level_wclk),
.rd_clk(rclk),.dout({dummy,dataout}),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
.wr_clk(wclk),.din(data_in_wide),.full(full),.wr_en(write),.wr_data_count(level_wclk),
.rd_clk(rclk),.dout(data_out_wide),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
end
endgenerate
assign occupied = {{(16-SIZE-1){1'b0}},level_rclk};
assign space = ((1<<SIZE)+1)-level_wclk;

5
fpga/top/UmTRX/u2plus_umtrx_v2.v
View File

@@ -31,11 +31,9 @@ module u2plus_umtrx_v2
input RX2IQSEL,
input [11:0] RX2D,
// DAC 1
output TX1EN,
output reg TX1IQSEL,
output reg [11:0] TX1D,
// DAC 2
output TX2EN,
output reg TX2IQSEL,
output reg [11:0] TX2D,
//LMS 1 Control
@@ -178,9 +176,6 @@ wire DivSw1, DivSw2;
wire [11:0] dac1_a, dac1_b, dac2_a, dac2_b;
wire dac1_strobe, dac2_strobe;
assign TX1EN = 1'b1;
assign TX2EN = 1'b1;
always @(posedge lms_clk) begin
if (dac1_strobe == 1'b1)
TX1D_reg <= dac1_a; //DAC_I signal

2
host/umtrx_impl.cpp
View File

@@ -387,7 +387,7 @@ umtrx_impl::umtrx_impl(const device_addr_t &device_addr)
}
umtrx_impl::~umtrx_impl(void){
//TODO
}
void umtrx_impl::set_mb_eeprom(const uhd::i2c_iface::sptr &iface, const uhd::usrp::mboard_eeprom_t &eeprom)