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fpga: fix DCSYNC clock to 541.66 kHz

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This commit is contained in:
Sergey Kostanbaev
2015-03-12 20:35:25 +03:00
parent 4e3edded07
commit a37e4c74de
1 changed files with 1 additions and 1 deletions
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2
fpga/top/UmTRX/u2plus_umtrx_v2.v
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@@ -323,7 +323,7 @@ wire DivSw1, DivSw2;
reg [5:0] dc_count;
always @(posedge lms_clk) begin
if (en_dc_sync_o == 1'b1) begin
if (dc_count == 24) begin
if (dc_count == 23) begin
dcsync_o <= ~dcsync_o;
dc_count <= 0;
end else