Add PA control logic

fpga/top/UmTRX/u2plus_umtrx_v2.ucf

@@ -227,6 +227,13 @@ NET "AUX_XX" LOC = AA6; // empty awhile
 NET "AUX_SCL" LOC = AB7;//  I2C clock (teperature sensor etc.)
 NET "AUX_SDA" LOC = AB10;//  I2C data (teperature sensor etc.)
 
+## PA control
+NET "ENPA2"   LOC = AB21;
+NET "ENPA1"   LOC = AA21;
+NET "LOWPA"   LOC = Y12;
+#NET "DC_SYNC" LOC = AA6;
+
+
 ## LEDS
 NET "leds[1]" LOC = Y3;
 NET "leds[2]" LOC = W4;
@@ -234,7 +241,7 @@ NET "leds[3]" LOC = AB2;
 NET "leds[4]" LOC = Y4;
 NET "leds[5]" LOC = AA2;
 NET "led_stat" LOC = AB3; // output for clock status (or something else) front panel LED !!!
-                          // was stupid "master clock" LED indicator
+			  // was stupid "master clock" LED indicator
 
 ### Debug  // a lot changes !!!
 NET "debug[0]" LOC = D22;
@@ -274,7 +281,7 @@ NET "debug_clk_n" LOC = L19;// was "debug_clk[1]" LOC = N16; !!!
 
 
 // #NET "CLK_FPGA_N" IOSTANDARD = LVPECL_25;//  LVCMOS25 - UNUSED  !!!
-#NET "CLK_FPGA" IOSTANDARD = LVCMOS25;// !!! 
+#NET "CLK_FPGA" IOSTANDARD = LVCMOS25;// !!!
 
 NET "FPGA_RESET" IOSTANDARD = LVCMOS33;
 NET "ETH_LED" IOSTANDARD = LVCMOS33;
@@ -314,6 +321,11 @@ NET "TXD[1]" IOSTANDARD = LVCMOS33;// FPGA input <- FTDI input  !!! in v1a was o
 NET "TXD[2]" IOSTANDARD = LVCMOS33;// FPGA input <- GPS input  !!! in v1a was output  !!!
 NET "TXD[3]" IOSTANDARD = LVCMOS33;
 
+NET "enpa2"   IOSTANDARD = LVCMOS33;
+NET "enpa1"   IOSTANDARD = LVCMOS33;
+NET "lowpa"   IOSTANDARD = LVCMOS33;
+#NET "DC_SYNC" IOSTANDARD = LVCMOS33;
+
 NET "DivSw1_N" IOSTANDARD = LVCMOS25;
 NET "DivSw1_P" IOSTANDARD = LVCMOS25;
 NET "DivSw2_N" IOSTANDARD = LVCMOS25;
@@ -337,4 +349,4 @@ NET "CLK_TO_MAC" TNM_NET = "CLK_TO_MAC";
 TIMESPEC TS_clk_to_mac = PERIOD "CLK_TO_MAC" 8 ns HIGH 50 %;
 
 NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK";
-TIMESPEC TS_GMII_RX_CLK = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %;
+TIMESPEC TS_GMII_RX_CLK = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %;

fpga/top/UmTRX/u2plus_umtrx_v2.v

@@ -77,6 +77,11 @@ module u2plus_umtrx_v2
    inout AUX_SCL,
    inout AUX_SDA,
 
+   //PA control
+   output ENPA2,
+   output ENPA1,
+   output LOWPA,
+
    // PPS
    input PPS_IN,
    output GPS_ON,
@@ -305,7 +310,11 @@ wire DivSw1, DivSw2;
    assign GPS_ON = 1'b1;
    assign pps = PPS_IN;
 
-   
+   wire enpa2_o, enpa1_o, lowpa_o;
+   OBUF enpa2_pin (.I(enpa2_o),.O(ENPA2));
+   OBUF enpa1_pin (.I(enpa1_o),.O(ENPA1));
+   OBUF lowpa_pin (.I(lowpa_o),.O(LOWPA));
+
    umtrx_core u2p_c(
 		     .sys_clk           (dsp_clk),
 		     .dsp_clk           (lms_clk),
@@ -370,6 +379,10 @@ wire DivSw1, DivSw2;
 //Diversity switches
 		     .DivSw1(DivSw1),
 		     .DivSw2(DivSw2),
+//PA control
+		     .enpa2(enpa2_o),
+		     .enpa1(enpa1_o),
+		     .lowpa(lowpa_o),
 `ifndef NO_EXT_FIFO
 		     .RAM_D_po          (RAM_D_po),
 		     .RAM_D_pi          (RAM_D_pi),

fpga/top/UmTRX/umtrx_core.v

@@ -107,6 +107,11 @@ module umtrx_core
    input aux_ld1,
    input aux_ld2,
 
+   //PA control
+   output enpa2,
+   output enpa1,
+   output lowpa,
+
 `ifndef NO_EXT_FIFO
    // External RAM
    input [35:0] RAM_D_pi,
@@ -547,9 +552,9 @@ module umtrx_core
    // Output control lines
    wire 	 phy_reset;
    assign 	 PHY_RESETn = ~phy_reset;
-   
+
    setting_reg #(.my_addr(SR_MISC+0),.width(2)) sr_lms_res
-     (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),.in(set_data),.out(lms_res),.changed());
+     (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),.in(set_data),.out({enpa2, enpa1, lowpa, lms_res}),.changed());
 
    setting_reg #(.my_addr(SR_MISC+1),.width(1)) sr_clear_sfc
      (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.changed(sfc_clear));