Add --dump & --erase options for EEPROM

Fix 4DDC version
Host: Support multiple DSPs connection to a single LMS.
2025-11-02 13:03:13 +00:00 · 2014-10-27 11:47:38 -04:00 · 2014-10-27 11:47:16 -04:00 · 2013-08-22 19:37:26 +04:00 · 2013-08-22 19:37:26 +04:00 · 2013-08-22 19:37:25 +04:00
17 changed files with 1122 additions and 856 deletions
--- a/firmware/zpu/apps/txrx_uhd.c
+++ b/firmware/zpu/apps/txrx_uhd.c
@@ -71,14 +71,18 @@ static void handle_udp_data_packet(
        sr_rx_ctrl1->time_ticks = 0; //latch the command
        break;

-    case USRP2_UDP_TX_DSP0_PORT:
-        //end async update packets per second
-        sr_tx_ctrl0->cyc_per_up = 0;
+    case USRP2_UDP_RX_DSP0_2_PORT:
+        //the end continuous streaming command
+        sr_rx_ctrl0_2->cmd = 1 << 31 | 1 << 28; //no samples now
+        sr_rx_ctrl0_2->time_secs = 0;
+        sr_rx_ctrl0_2->time_ticks = 0; //latch the command
        break;

-    case USRP2_UDP_TX_DSP1_PORT:
-        //end async update packets per second
-        sr_tx_ctrl1->cyc_per_up = 0;
+    case USRP2_UDP_RX_DSP1_2_PORT:
+        //the end continuous streaming command
+        sr_rx_ctrl1_2->cmd = 1 << 31 | 1 << 28; //no samples now
+        sr_rx_ctrl1_2->time_secs = 0;
+        sr_rx_ctrl1_2->time_ticks = 0; //latch the command
        break;

    default: return;
@@ -95,11 +99,11 @@ static void handle_udp_data_packet(
        which = 2;
        break;

-    case USRP2_UDP_TX_DSP0_PORT:
+    case USRP2_UDP_RX_DSP0_2_PORT:
        which = 1;
        break;

-    case USRP2_UDP_TX_DSP1_PORT:
+    case USRP2_UDP_RX_DSP1_2_PORT:
        which = 3;
        break;

@@ -355,15 +359,15 @@ main(void)

  //1) register the addresses into the network stack
  register_addrs(ethernet_mac_addr(), get_ip_addr());
-  pkt_ctrl_program_inspector(get_ip_addr(), USRP2_UDP_TX_DSP0_PORT, USRP2_UDP_TX_DSP1_PORT);
+  pkt_ctrl_program_inspector(get_ip_addr());

  //2) register callbacks for udp ports we service
  init_udp_listeners();
  register_udp_listener(USRP2_UDP_CTRL_PORT, handle_udp_ctrl_packet);
  register_udp_listener(USRP2_UDP_RX_DSP0_PORT, handle_udp_data_packet);
  register_udp_listener(USRP2_UDP_RX_DSP1_PORT, handle_udp_data_packet);
-  register_udp_listener(USRP2_UDP_TX_DSP0_PORT, handle_udp_data_packet);
-  register_udp_listener(USRP2_UDP_TX_DSP1_PORT, handle_udp_data_packet);
+  register_udp_listener(USRP2_UDP_RX_DSP0_2_PORT, handle_udp_data_packet);
+  register_udp_listener(USRP2_UDP_RX_DSP1_2_PORT, handle_udp_data_packet);
  
 #ifdef USRP2P
 #ifndef NO_FLASH
--- a/firmware/zpu/lib/memory_map.h
+++ b/firmware/zpu/lib/memory_map.h
@@ -252,22 +252,19 @@ typedef struct {
 #define SR_RX_FRONT  20   // 5
 #define SR_RX_FRONT1  25   // 5
 #endif
-#define SR_RX_CTRL0  32   // 9
-#define SR_RX_DSP0   48   // 7
-#define SR_RX_CTRL1  80   // 9
-#define SR_RX_DSP1   96   // 7
+#define SR_RX_CTRL0  32   // 10
+#define SR_RX_DSP0   42   // 7
+#define SR_RX_CTRL1  49   // 10
+#define SR_RX_DSP1   59   // 7
+#define SR_RX_CTRL0_2  66   // 10
+#define SR_RX_DSP0_2   76   // 7
+#define SR_RX_CTRL1_2  117   // 10
+#define SR_RX_DSP1_2   127   // 7

 #ifndef UMTRX
 #define SR_TX_FRONT 128   // ?
 #define SR_TX_CTRL  144   // 6
 #define SR_TX_DSP   160   // 5
-#else
-#define SR_TX_FRONT0 110   // ?
-#define SR_TX_CTRL0  126   // 6
-#define SR_TX_DSP0   135   // 5
-#define SR_TX_FRONT1 145   // ?
-#define SR_TX_CTRL1  161   // 6
-#define SR_TX_DSP1   170   // 5
 #endif

 #define SR_UDP_SM   192   // 64
@@ -349,8 +346,6 @@ typedef struct {
  volatile uint32_t     packets_per_up;
 } sr_tx_ctrl_t;

-#define sr_tx_ctrl0 ((sr_tx_ctrl_t *) _SR_ADDR(SR_TX_CTRL0))
-#define sr_tx_ctrl1 ((sr_tx_ctrl_t *) _SR_ADDR(SR_TX_CTRL1))

 // --- VITA RX CTRL regs ---
 typedef struct {
@@ -363,6 +358,8 @@ typedef struct {

 #define sr_rx_ctrl0 ((sr_rx_ctrl_t *) _SR_ADDR(SR_RX_CTRL0))
 #define sr_rx_ctrl1 ((sr_rx_ctrl_t *) _SR_ADDR(SR_RX_CTRL1))
+#define sr_rx_ctrl0_2 ((sr_rx_ctrl_t *) _SR_ADDR(SR_RX_CTRL0_2))
+#define sr_rx_ctrl1_2 ((sr_rx_ctrl_t *) _SR_ADDR(SR_RX_CTRL1_2))

 // ----------------------------------------------------------------
 // VITA49 64 bit time (write only)
--- a/firmware/zpu/lib/pkt_ctrl.c
+++ b/firmware/zpu/lib/pkt_ctrl.c
@@ -38,10 +38,8 @@
 #define CPU_CTRL_WR_START (1 << 3)

 void pkt_ctrl_program_inspector(
-    const struct ip_addr *ip_addr, uint16_t data_port0, uint16_t data_port1
-){
+    const struct ip_addr *ip_addr){
    router_ctrl->ip_addr = ip_addr->addr;
-    router_ctrl->data_ports = data_port0 | ((uint32_t)(data_port1) << 16);
 }

 void pkt_ctrl_set_routing_mode(pkt_ctrl_routing_mode_t mode){
--- a/firmware/zpu/lib/pkt_ctrl.h
+++ b/firmware/zpu/lib/pkt_ctrl.h
@@ -30,8 +30,7 @@ typedef enum {

 //! Program the decision values into the packet inspector
 void pkt_ctrl_program_inspector(
-    const struct ip_addr *ip_addr, uint16_t data_port0, uint16_t data_port1
-);
+    const struct ip_addr *ip_addr);

 //! Set the routing mode for this device
 void pkt_ctrl_set_routing_mode(pkt_ctrl_routing_mode_t mode);
--- a/firmware/zpu/usrp2p/udp_fw_update.c
+++ b/firmware/zpu/usrp2p/udp_fw_update.c
@@ -82,8 +82,12 @@ void handle_udp_fw_update_packet(struct socket_address src, struct socket_addres
    sr_rx_ctrl1->cmd = 1 << 31 | 1 << 28; //no samples now
    sr_rx_ctrl1->time_secs = 0;
    sr_rx_ctrl1->time_ticks = 0; //latch the command
-    sr_tx_ctrl0->cyc_per_up = 0;
-    sr_tx_ctrl1->cyc_per_up = 0;
+    sr_rx_ctrl0_2->cmd = 1 << 31 | 1 << 28; //no samples now
+    sr_rx_ctrl0_2->time_secs = 0;
+    sr_rx_ctrl0_2->time_ticks = 0; //latch the command
+    sr_rx_ctrl1_2->cmd = 1 << 31 | 1 << 28; //no samples now
+    sr_rx_ctrl1_2->time_secs = 0;
+    sr_rx_ctrl1_2->time_ticks = 0; //latch the command
    break;

  case USRP2_FW_UPDATE_ID_WATS_TEH_FLASH_INFO_LOL: //query sector size, memory size so the host can mind the boundaries
--- a/fpga/usrp2/fifo/packet_router.v
+++ b/fpga/usrp2/fifo/packet_router.v
@@ -52,15 +52,15 @@ module packet_router
        input [35:0] ser_inp_data, input ser_inp_valid, output ser_inp_ready,
        input [35:0] dsp0_inp_data, input dsp0_inp_valid, output dsp0_inp_ready,
        input [35:0] dsp1_inp_data, input dsp1_inp_valid, output dsp1_inp_ready,
+        input [35:0] dsp2_inp_data, input dsp2_inp_valid, output dsp2_inp_ready,
+        input [35:0] dsp3_inp_data, input dsp3_inp_valid, output dsp3_inp_ready,
        input [35:0] eth_inp_data, input eth_inp_valid, output eth_inp_ready,
-        input [35:0] err_inp_data, input err_inp_valid, output err_inp_ready,

        // Output Interfaces (out of router)
        output [35:0] ser_out_data, output ser_out_valid, input ser_out_ready,
        output [35:0] dsp_out_data, output dsp_out_valid, input dsp_out_ready,
 `ifdef LMS602D_FRONTEND
        output dsp1_out_valid, input dsp1_out_ready,
-        input [35:0] err_inp1_data, input err_inp1_valid, output err_inp1_ready,
 `endif // !`ifdef LMS602D_FRONTEND
        output [35:0] eth_out_data, output eth_out_valid, input eth_out_ready
    );
@@ -195,38 +195,11 @@ module packet_router
    wire [35:0] _combiner0_data, _combiner1_data;
    wire        _combiner0_valid, _combiner1_valid;
    wire        _combiner0_ready, _combiner1_ready;
+    wire [35:0] _combiner2_data, _combiner3_data;
+    wire        _combiner2_valid, _combiner3_valid;
+    wire        _combiner2_ready, _combiner3_ready;

-`ifdef LMS602D_FRONTEND
-    wire [35:0] _combiner0_0_data;
-    wire        _combiner0_0_valid;
-    wire        _combiner0_0_ready;
-
-    fifo36_mux #(.prio(0)) // No priority, fair sharing
-     _com_output_combiner0_0(
-        .clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
-        .data0_i(err_inp_data), .src0_rdy_i(err_inp_valid), .dst0_rdy_o(err_inp_ready),
-        .data1_i(err_inp1_data), .src1_rdy_i(err_inp1_valid), .dst1_rdy_o(err_inp1_ready),
-        .data_o(_combiner0_0_data), .src_rdy_o(_combiner0_0_valid), .dst_rdy_i(_combiner0_0_ready)
-    );
-
-    fifo36_mux #(.prio(0)) // No priority, fair sharing
-     _com_output_combiner0(
-        .clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
-        .data0_i(_combiner0_0_data), .src0_rdy_i(_combiner0_0_valid), .dst0_rdy_o(_combiner0_0_ready),
-        .data1_i(cpu_inp_data), .src1_rdy_i(cpu_inp_valid), .dst1_rdy_o(cpu_inp_ready),
-        .data_o(_combiner0_data), .src_rdy_o(_combiner0_valid), .dst_rdy_i(_combiner0_ready)
-    );
-`else
-    
-    fifo36_mux #(.prio(0)) // No priority, fair sharing
-     _com_output_combiner0(
-        .clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
-        .data0_i(err_inp_data), .src0_rdy_i(err_inp_valid), .dst0_rdy_o(err_inp_ready),
-        .data1_i(cpu_inp_data), .src1_rdy_i(cpu_inp_valid), .dst1_rdy_o(cpu_inp_ready),
-        .data_o(_combiner0_data), .src_rdy_o(_combiner0_valid), .dst_rdy_i(_combiner0_ready)
-    );
-`endif // !`ifdef LMS602D_FRONTEND
-
+// DSP RX for LMS 0
    fifo36_mux #(.prio(0)) // No priority, fair sharing
     _com_output_combiner1(
        .clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
@@ -235,11 +208,28 @@ module packet_router
        .data_o(_combiner1_data), .src_rdy_o(_combiner1_valid), .dst_rdy_i(_combiner1_ready)
    );

+// DSP RX for LMS 1
+    fifo36_mux #(.prio(0)) // No priority, fair sharing
+     _com_output_combiner2(
+        .clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
+        .data0_i(dsp2_inp_data), .src0_rdy_i(dsp2_inp_valid), .dst0_rdy_o(dsp2_inp_ready),
+        .data1_i(dsp3_inp_data), .src1_rdy_i(dsp3_inp_valid), .dst1_rdy_o(dsp3_inp_ready),
+        .data_o(_combiner2_data), .src_rdy_o(_combiner2_valid), .dst_rdy_i(_combiner2_ready)
+    );
+
+    fifo36_mux #(.prio(0)) // No priority, fair sharing
+     _com_output_combiner3(
+        .clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
+        .data0_i(_combiner1_data), .src0_rdy_i(_combiner1_valid), .dst0_rdy_o(_combiner1_ready),
+        .data1_i(_combiner2_data), .src1_rdy_i(_combiner2_valid), .dst1_rdy_o(_combiner2_ready),
+        .data_o(_combiner3_data), .src_rdy_o(_combiner3_valid), .dst_rdy_i(_combiner3_ready)
+    );
+
    fifo36_mux #(.prio(1)) // Give priority to err/cpu over dsp
     com_output_source(
        .clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
-        .data0_i(_combiner0_data), .src0_rdy_i(_combiner0_valid), .dst0_rdy_o(_combiner0_ready),
-        .data1_i(_combiner1_data), .src1_rdy_i(_combiner1_valid), .dst1_rdy_o(_combiner1_ready),
+        .data0_i(cpu_inp_data), .src0_rdy_i(cpu_inp_valid), .dst0_rdy_o(cpu_inp_ready),
+        .data1_i(_combiner3_data), .src1_rdy_i(_combiner3_valid), .dst1_rdy_o(_combiner3_ready),
        .data_o(udp_out_data), .src_rdy_o(udp_out_valid), .dst_rdy_i(udp_out_ready)
    );

@@ -322,7 +312,6 @@ module packet_router
        //inputs to the router (12)
        dsp0_inp_ready, dsp0_inp_valid,
        dsp1_inp_ready, dsp1_inp_valid,
-        err_inp_ready, err_inp_valid,
        ser_inp_ready, ser_inp_valid,
        eth_inp_ready, eth_inp_valid,
        cpu_inp_ready, cpu_inp_valid,
--- a/fpga/usrp2/sdr_lib/frontend_sw.v
+++ b/fpga/usrp2/sdr_lib/frontend_sw.v
@@ -14,58 +14,76 @@
 // along with this program.  If not, see <http://www.gnu.org/licenses/>.

 module frontend_sw
-  #(parameter BASE=0)
+  #(parameter BASE=0,
+    parameter WIDTH=4)
   (input clk, input rst,
    input set_stb, input [7:0] set_addr, input [31:0] set_data,
    input [23:0] i_0_in, input [23:0] q_0_in, 
    input [23:0] i_1_in, input [23:0] q_1_in,
    input run_0_in, input run_1_in,
+    input run_2_in, input run_3_in,
    input adc_ovf_i_0_in, input adc_ovf_q_0_in,
    input adc_ovf_i_1_in, input adc_ovf_q_1_in,    
-    output reg [23:0] i_0_mux, output reg [23:0] q_0_mux, 
-    output reg [23:0] i_1_mux, output reg [23:0] q_1_mux,
-    output reg run_0_mux, output reg run_1_mux,
-    output reg adc_ovf_i_0_mux, output reg adc_ovf_q_0_mux,
-    output reg adc_ovf_i_1_mux, output reg adc_ovf_q_1_mux);
+    output [23:0] i_0_mux, output [23:0] q_0_mux, 
+    output [23:0] i_1_mux, output [23:0] q_1_mux,
+    output [23:0] i_2_mux, output [23:0] q_2_mux, 
+    output [23:0] i_3_mux, output [23:0] q_3_mux,
+    output run_0_mux, output run_1_mux,
+    output run_2_mux, output run_3_mux,
+    output adc_ovf_i_0_mux, output adc_ovf_q_0_mux,
+    output adc_ovf_i_1_mux, output adc_ovf_q_1_mux,
+    output adc_ovf_i_2_mux, output adc_ovf_q_2_mux,
+    output adc_ovf_i_3_mux, output adc_ovf_q_3_mux);

-   wire front_sw;
-   setting_reg #(.my_addr(BASE),.width(1), .at_reset(32'd0)) sr_front_sw
+   wire [WIDTH-1:0] front_sw;
+   setting_reg #(.my_addr(BASE),.width(WIDTH), .at_reset(32'd0)) sr_front_sw
     (.clk(clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),.in(set_data),.out(front_sw),.changed());
     
+   reg [23:0] i_mux [WIDTH-1:0], q_mux [WIDTH-1:0];
+   reg [WIDTH-1:0] run_mux ;
+   reg [WIDTH-1:0] adc_ovf_i_mux, adc_ovf_q_mux ;
+   wire [WIDTH-1:0] run_in;
+   
+   assign i_0_mux = i_mux[0];   assign q_0_mux = q_mux[0]; 
+   assign i_1_mux = i_mux[1];   assign q_1_mux = q_mux[1];
+   assign i_2_mux = i_mux[2];   assign q_2_mux = q_mux[2];
+   assign i_3_mux = i_mux[3];   assign q_3_mux = q_mux[3];
+
+   assign run_0_mux = run_mux[0];   assign run_1_mux = run_mux[1];
+   assign run_2_mux = run_mux[2];   assign run_3_mux = run_mux[3];
+   
+   assign run_in[0] = run_0_in;   assign run_in[1] = run_1_in;
+   assign run_in[2] = run_2_in;   assign run_in[3] = run_3_in;
+   
+   assign adc_ovf_i_0_mux = adc_ovf_i_mux[0];   assign adc_ovf_q_0_mux = adc_ovf_q_mux[0];
+   assign adc_ovf_i_1_mux = adc_ovf_i_mux[1];   assign adc_ovf_q_1_mux = adc_ovf_q_mux[1];
+   assign adc_ovf_i_2_mux = adc_ovf_i_mux[2];   assign adc_ovf_q_2_mux = adc_ovf_q_mux[2];
+   assign adc_ovf_i_3_mux = adc_ovf_i_mux[3];   assign adc_ovf_q_3_mux = adc_ovf_q_mux[3];
+
+  genvar i;
+  generate for (i=0; i<WIDTH; i=i+1)
+  begin
   always @(posedge clk)
-      if(~front_sw)
-         begin
-            i_0_mux <= i_0_in;
-            q_0_mux <= q_0_in;
-            
-            i_1_mux <= i_1_in;
-            q_1_mux <= q_1_in;
-            
-            run_0_mux <= run_0_in;
-            run_1_mux <= run_1_in;
-            
-            adc_ovf_i_0_mux <= adc_ovf_i_0_in;
-            adc_ovf_q_0_mux <= adc_ovf_q_0_in;
-            
-            adc_ovf_i_1_mux <= adc_ovf_i_1_in;
-            adc_ovf_q_1_mux <= adc_ovf_q_1_in;
-         end
-      else
-         begin
-            i_0_mux <= i_1_in;
-            q_0_mux <= q_1_in;
-            
-            i_1_mux <= i_0_in;
-            q_1_mux <= q_0_in;
-            
-            run_0_mux <= run_1_in;
-            run_1_mux <= run_0_in;
-            
-            adc_ovf_i_0_mux <= adc_ovf_i_1_in;
-            adc_ovf_q_0_mux <= adc_ovf_q_1_in;
-            
-            adc_ovf_i_1_mux <= adc_ovf_i_0_in;
-            adc_ovf_q_1_mux <= adc_ovf_q_0_in;
-         end
-     
+   begin
+      if(~front_sw[i])
+            begin
+               i_mux[i] <= i_0_in;
+               q_mux[i] <= q_0_in;
+               
+               adc_ovf_i_mux[i] <= adc_ovf_i_0_in;
+               adc_ovf_q_mux[i] <= adc_ovf_q_0_in;
+            end
+         else
+            begin
+               i_mux[i] <= i_1_in;
+               q_mux[i] <= q_1_in;
+                              
+               adc_ovf_i_mux[i] <= adc_ovf_i_1_in;
+               adc_ovf_q_mux[i] <= adc_ovf_q_1_in;
+            end
+         run_mux[i] <= run_in[i];
+   end
+  end
+  endgenerate
+
 endmodule
--- a/fpga/usrp2/top/N2x0/bootloader_umtrx.rmi
+++ b/fpga/usrp2/top/N2x0/bootloader_umtrx.rmi
@@ -1,5 +1,5 @@
-defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_d5a90400_3a0b0b80_80e2d00c_82700b0b_0b0b0b0b;
-defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_800c0400_880c840c_80d5f32d_88080b0b_80088408;
+defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_dfe30400_3a0b0b80_80edcc0c_82700b0b_0b0b0b0b;
+defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_800c0400_880c840c_80e0ad2d_88080b0b_80088408;
 defparam bootram.RAM0.INIT_02=256'h00000000_00000000_04000000_ffff0652_832b2a83_81058205_72830609_71fd0608;
 defparam bootram.RAM0.INIT_03=256'h83a70400_0b0b0b0b_7383ffff_2b2b0906_05820583_83060981_83ffff73_71fd0608;
 defparam bootram.RAM0.INIT_04=256'h00000000_00000000_53510400_070a8106_73097306_09060906_72057373_72098105;
@@ -18,427 +18,427 @@ defparam bootram.RAM0.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_
 defparam bootram.RAM0.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_04000000_05055351_72720981;
 defparam bootram.RAM0.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_07535104_73730906_72097206;
 defparam bootram.RAM0.INIT_13=256'h00000000_00000000_04000000_81ff0652_1010102a_81058305_72830609_71fc0608;
-defparam bootram.RAM0.INIT_14=256'h00000000_00000000_88aa0400_060b0b0b_10100508_bc738306_0b0b80e2_71fc0608;
-defparam bootram.RAM0.INIT_15=256'h00000000_0c510400_0c840c80_80085688_ca2d5050_0b0b80cc_88087575_80088408;
-defparam bootram.RAM0.INIT_16=256'h00000000_0c510400_0c840c80_80085688_fc2d5050_0b0b80cd_88087575_80088408;
+defparam bootram.RAM0.INIT_14=256'h00000000_00000000_88aa0400_060b0b0b_10100508_b8738306_0b0b80ed_71fc0608;
+defparam bootram.RAM0.INIT_15=256'h00000000_0c510400_0c840c80_80085688_842d5050_0b0b80d7_88087575_80088408;
+defparam bootram.RAM0.INIT_16=256'h00000000_0c510400_0c840c80_80085688_b62d5050_0b0b80d8_88087575_80088408;
 defparam bootram.RAM0.INIT_17=256'h04000000_07515151_05ff0506_73097274_70547106_8106ff05_0509060a_72097081;
 defparam bootram.RAM0.INIT_18=256'h51040000_06075151_7405ff05_06730972_05705471_098106ff_0509060a_72097081;
 defparam bootram.RAM0.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_05ff0504;
-defparam bootram.RAM0.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_51040000_80e2cc0c_810b0b0b;
+defparam bootram.RAM0.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_51040000_80edc80c_810b0b0b;
 defparam bootram.RAM0.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_04000000_71810552;
 defparam bootram.RAM0.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
 defparam bootram.RAM0.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_04000000_10100552_02840572;
 defparam bootram.RAM0.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
 defparam bootram.RAM0.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_020d0400_05715351_717105ff;
-defparam bootram.RAM0.INIT_20=256'h10101010_10101010_10101010_10101010_10101010_10101010_cdf03f04_82813f80;
+defparam bootram.RAM0.INIT_20=256'h10101010_10101010_10101010_10101010_10101010_10101010_d8aa3f04_82813f80;
 defparam bootram.RAM0.INIT_21=256'hfc060c51_102b0772_83051010_06098105_ff067383_51047381_10101053_10101010;
 defparam bootram.RAM0.INIT_22=256'h51535104_72ed3851_0a100a53_71105272_09720605_8106ff05_72728072_51043c04;
-defparam bootram.RAM0.INIT_23=256'h800b80e3_a80c82a0_0b0b80e3_8380800b_822ebd38_80e2d008_802ea438_80e2cc08;
-defparam bootram.RAM0.INIT_24=256'h0b80e3ac_80808280_e3a80cf8_0b0b0b80_808080a4_b00c04f8_800b80e3_ac0c8290;
-defparam bootram.RAM0.INIT_25=256'h940b80e3_80c0a880_80e3a80c_8c0b0b0b_80c0a880_e3b00c04_84800b80_0cf88080;
-defparam bootram.RAM0.INIT_26=256'h70085252_80e2d808_5170a738_80e3b433_04ff3d0d_80e3b00c_80d6a40b_ac0c0b0b;
-defparam bootram.RAM0.INIT_27=256'hb434833d_810b80e3_5270ee38_08700852_2d80e2d8_e2d80c70_38841280_70802e94;
-defparam bootram.RAM0.INIT_28=256'h38823d0d_09810685_800b802e_0b0b0b0b_802e8e38_80e3a408_3d0d0b0b_0d040480;
-defparam bootram.RAM0.INIT_29=256'h3d225a79_80d33895_0d685b7a_0404ee3d_3f823d0d_0b0bf5d4_e3a4510b_040b0b80;
-defparam bootram.RAM0.INIT_2A=256'h2e973881_79838086_3881e439_80842e8e_8b387983_83808524_80c23879_8380852e;
-defparam bootram.RAM0.INIT_2B=256'h7a81e2c4_81e2c00c_39890a0b_e1880c99_840c7a81_0c7a81e1_0b81e180_da39890a;
-defparam bootram.RAM0.INIT_2C=256'h2e9e3879_79838085_973d225a_7c2eab38_0c805c7a_7a81e4d0_c80c8639_0c7a81e2;
-defparam bootram.RAM0.INIT_2D=256'h815c923d_38818039_80862e86_825c7983_38818c39_80842e92_8b387983_83808524;
-defparam bootram.RAM0.INIT_2E=256'h3d415e5c_0b883d99_5b5f4080_0284057d_ff3f8008_a7f43f88_84055241_7053963d;
-defparam bootram.RAM0.INIT_2F=256'h7d055b5b_7b1d963d_901f5e5c_ef38800b_5c887c26_7b34811c_5b5b7933_7b1d7f1d;
-defparam bootram.RAM0.INIT_30=256'h811c5c86_79337b34_601d5b5b_5e5c7b1d_800b881f_7c26ed38_811c5c88_79337b34;
-defparam bootram.RAM0.INIT_31=256'h3d0d04ee_98ea3f94_7c26ef38_811c5c86_79337b34_611d5b5b_805c7b1e_7c26ef38;
-defparam bootram.RAM0.INIT_32=256'h75538b52_802e8c38_2e943875_0856758b_279c3877_5a588379_84120859_3d0d686a;
-defparam bootram.RAM0.INIT_33=256'h8b5ba05c_e43fa057_d6f85193_53a45280_268e3878_f55778a3_93f73f80_80d6a851;
-defparam bootram.RAM0.INIT_34=256'h888d3f80_0480d55c_05567508_2980d8e8_91387584_758d2682_ff981756_8818085d;
-defparam bootram.RAM0.INIT_35=256'h962a8480_32703070_183380f2_2e923894_577580f2_33568880_fb399518_08085e81;
-defparam bootram.RAM0.INIT_36=256'h83388157_5775772e_97193357_0852800b_08538c18_33549018_76559618_06595156;
-defparam bootram.RAM0.INIT_37=256'h568bbd3f_8c193352_3dea0553_33705495_b3398d18_80d35c81_3f80085f_7651958d;
-defparam bootram.RAM0.INIT_38=256'hb5053480_75028405_3f80c85c_52568cca_538c1933_70548e19_398d1833_80c95c94;
-defparam bootram.RAM0.INIT_39=256'h0476085f_58567508_058c1908_2980d9a0_c2387584_75852680_33ff0556_ff399418;
-defparam bootram.RAM0.INIT_3A=256'h70084056_80e3b805_39768429_2277239b_a2399218_1808770c_5fa93990_ae397622;
-defparam bootram.RAM0.INIT_3B=256'h55943ddc_5c8c1808_785e80cc_d25cad39_710c5680_05901908_2980e3b8_8e397684;
-defparam bootram.RAM0.INIT_3C=256'ha439a05c_7826ed38_81185888_75337734_79055757_7719963d_833d5a58_0554800b;
-defparam bootram.RAM0.INIT_3D=256'h887826ed_34811858_57753377_3d790557_58771996_0b833d5a_dc055480_a455943d;
-defparam bootram.RAM0.INIT_3E=256'h2e9d38a0_843f7380_c4525491_705380d7_fd3d0d75_943d0d04_5199f63f_38838080;
-defparam bootram.RAM0.INIT_3F=256'h52735186_3f9539a0_ab3f99fe_3f81518e_725186b7_c0537252_2e843880_537387e8;
-defparam bootram.RAM1.INIT_00=256'h5187923f_3f80d7e4_3d0d828f_3d0d04fa_8e923f85_9e3f7351_52735186_a63f80c0;
-defparam bootram.RAM1.INIT_01=256'hf53f84dc_a7ff3f83_80e3d40c_ac3f810b_d8a05190_3f8b5280_805190b5_885280d8;
-defparam bootram.RAM1.INIT_02=256'h84cd3f80_3f869d3f_08518efe_84d93f80_3f86a93f_08518ee4_84863f80_3f82f13f;
-defparam bootram.RAM1.INIT_03=256'h3f8cbf52_ef3f9395_8008518c_83808552_3f84bc3f_0851938b_3f735280_085483e8;
-defparam bootram.RAM1.INIT_04=256'hb2528380_93bd3f8a_83808651_3f8ab252_845193c7_b2528380_93d13f8a_83808051;
-defparam bootram.RAM1.INIT_05=256'hcc51a8b6_8ce63f8f_da3f8051_809251a3_93a93f83_83808251_3fbdaf52_855193b3;
-defparam bootram.RAM1.INIT_06=256'h55557382_088e0522_c9387680_08802e80_80085680_518cdd3f_883dfc05_3faadb3f;
-defparam bootram.RAM1.INIT_07=256'hd8cc518e_089a3880_c1ec3f80_90055180_c4528008_845380d8_8106ad38_fdee2e09;
-defparam bootram.RAM1.INIT_08=256'he23fa3ad_98e13f8b_74527551_e73f8839_3f735183_cd3f84ec_7052548d_dc3f9416;
-defparam bootram.RAM1.INIT_09=256'h5184853f_3f9f5280_8c3f86dc_85e03f8a_3f90a43f_3d0d84b5_ff9e39fe_3f8ad43f;
-defparam bootram.RAM1.INIT_0A=256'h885183c7_be3f8852_82ac5189_5183d43f_3f845284_ac5189cb_83e13f82_9f528051;
-defparam bootram.RAM1.INIT_0B=256'h3f80e451_805183ab_82539f52_5189a43f_ba3f82ac_52905183_89b13f90_3f82ac51;
-defparam bootram.RAM1.INIT_0C=256'h83a63f9f_9f529e51_8025df38_ff135372_5189883f_9e3f80e4_529c5183_89953f9f;
-defparam bootram.RAM1.INIT_0D=256'h88805381_80559054_fc3d0d88_843d0d04_810b800c_81e0840c_823f890b_52815183;
-defparam bootram.RAM1.INIT_0E=256'h8f933f80_82528151_54888053_88805590_518d8e3f_5280d9b8_ac3f8008_5281518f;
-defparam bootram.RAM1.INIT_0F=256'h80537276_81705654_787a5757_04fa3d0d_0c863d0d_3f810b80_d4518cf5_085280d9;
-defparam bootram.RAM1.INIT_10=256'h1353df39_38805581_81ff2e83_71335271_83388054_5270802e_17703352_279e3872;
-defparam bootram.RAM1.INIT_11=256'h5380d9f4_e3dc3486_0d810b80_0d04fe3d_800c883d_38815170_70802e83_74740751;
-defparam bootram.RAM1.INIT_12=256'h34865487_0b80e3dc_74bc3881_e3dc3355_f93d0d80_843d0d04_51bcf33f_5280e2e0;
-defparam bootram.RAM1.INIT_13=256'hf43f8008_527551fe_2e9c3886_06557480_800881ff_51abfe3f_825280d0_3d705456;
-defparam bootram.RAM1.INIT_14=256'h810b80e3_893d0d04_e00b800c_a93f80e2_e2e051bc_53755280_748c3886_81ff0655;
-defparam bootram.RAM1.INIT_15=256'h8454873d_80e3d834_b938810b_d8335574_3d0d80e3_dc0c04fb_f00880e2_d83480d9;
-defparam bootram.RAM1.INIT_16=256'h51fe923f_873dfc05_99388452_5574802e_0881ff06_ab9f3f80_5280d051_fc05538c;
-defparam bootram.RAM1.INIT_17=256'h56845475_fb3d0d77_873d0d04_dc0b800c_dc0c80e2_387580e2_06557486_800881ff;
-defparam bootram.RAM1.INIT_18=256'h80e3d834_dc0c810b_750880e2_802e8d38_ff065574_3f800881_d051a9e5_538c5280;
-defparam bootram.RAM1.INIT_19=256'he08c0c51_e3e00c81_06077080_80e3e008_73750671_3d0d7309_3d0d0480_74800c87;
-defparam bootram.RAM1.INIT_1A=256'h51823d0d_81e0980c_80e3e40c_08060770_7180e3e4_09737506_803d0d73_823d0d04;
-defparam bootram.RAM1.INIT_1B=256'h52805181_ff3d0d8a_843d0d04_3f72800c_805181c7_74705353_04fe3d0d_0481af3f;
-defparam bootram.RAM1.INIT_1C=256'h7481ff06_90388115_5472802e_81ff0654_56743370_0d777956_0d04fb3d_b63f833d;
-defparam bootram.RAM1.INIT_1D=256'h0d04fe3d_cd3f833d_73528051_04ff3d0d_0c873d0d_39800b80_81913fe5_53765255;
-defparam bootram.RAM1.INIT_1E=256'h73528051_04ff3d0d_0c843d0d_3f800b80_725180e7_bd3f8a52_705253ff_0d747653;
-defparam bootram.RAM1.INIT_1F=256'ha0298290_ff3d0d73_823d0d04_e2e81234_8f053380_0d725102_0d04803d_dd3f833d;
-defparam bootram.RAM1.INIT_20=256'h527251c6_e2e81333_0d805380_0d04fe3d_5351833d_7022720c_80d9fc05_80057510;
-defparam bootram.RAM1.INIT_21=256'h5654748a_3d0d7678_3d0d04fc_25e53884_13538273_51ce3f81_13335272_3f80e2ec;
-defparam bootram.RAM1.INIT_22=256'h29829080_de3f73a0_8d527351_81068738_72812e09_e8143353_953880e2_2e098106;
-defparam bootram.RAM1.INIT_23=256'h05881108_29829080_3d0d74a0_3d0d04fe_8c150c86_2ef83874_08537280_05548414;
-defparam bootram.RAM1.INIT_24=256'h0c80e2f4_0b81a888_ff3d0d80_843d0d04_5372800c_38901208_70802e85_5252ff53;
-defparam bootram.RAM1.INIT_25=256'hfd3d0d76_833d0d04_81a8880c_5181800b_81a8840c_0c70882a_0681a880_227081ff;
-defparam bootram.RAM1.INIT_26=256'h51515170_2a708106_90087086_863881a8_71802e81_53548151_97053355_78028805;
-defparam bootram.RAM1.INIT_27=256'h515170f1_70810651_0870812a_0c81a890_0b81a890_8c0c8190_810781a8_f1387210;
-defparam bootram.RAM1.INIT_28=256'h80e85171_802eb138_2eba3871_51517080_81325151_70810670_0870872a_3881a890;
-defparam bootram.RAM1.INIT_29=256'ha88c0851_70f13881_06515151_812a7081_a8900870_a8900c81_a0517081_812e8338;
-defparam bootram.RAM1.INIT_2A=256'h0d04fd3d_800c853d_a8900c70_80c00b81_81518839_1252cc39_055634ff_70747081;
-defparam bootram.RAM1.INIT_2B=256'h721081a8_5170f138_81065151_70862a70_81a89008_33555354_88059705_0d767802;
-defparam bootram.RAM1.INIT_2C=256'h51515170_2a708106_90087081_900c81a8_517081a8_84388190_5171802e_8c0c81d0;
-defparam bootram.RAM1.INIT_2D=256'h80c53873_3871802e_802e80cf_51515170_70813251_2a708106_90087087_f13881a8;
-defparam bootram.RAM1.INIT_2E=256'h81065151_70812a70_81a89008_81a8900c_38905170_71812e83_0c80d051_3381a88c;
-defparam bootram.RAM1.INIT_2F=256'hff135354_8e388114_5170802e_32515151_81067081_70872a70_81a89008_5170f138;
-defparam bootram.RAM1.INIT_30=256'h80537274_3d0d7554_3d0d04fd_70800c85_900c8051_c00b81a8_518a3980_ffb73981;
-defparam bootram.RAM1.INIT_31=256'h39853d0d_811353e2_7127f138_5180e5c7_70733151_81b8ac08_b8ac0852_259b3881;
-defparam bootram.RAM1.INIT_32=256'h0c80ee8c_0b82808c_80840cff_0cef0b82_0b828080_880c81e2_ff0b8280_04ff3d0d;
-defparam bootram.RAM1.INIT_33=256'h88087009_3d0d8280_3d0d04fb_25f13883_11517080_05540cff_e7727084_5287519d;
-defparam bootram.RAM1.INIT_34=256'h51730852_2e8f3872_06527180_55557476_0b80ee8c_52805381_71065851_82808c08;
-defparam bootram.RAM1.INIT_35=256'h3d0d7352_3d0d04ff_25dc3887_55538773_15761057_39811384_808c0c8f_712d7482;
-defparam bootram.RAM1.INIT_36=256'h8280880c_08707206_09828088_81722b70_75710c51_80ee8c05_38718429_7187269f;
-defparam bootram.RAM1.INIT_37=256'h3d0d0480_e0c80c83_c40c5281_700881e0_92052274_ff3d0d02_3d0d0404_53515283;
-defparam bootram.RAM1.INIT_38=256'h823d0d04_81e0cc0c_f338820b_5170802e_70840651_81b8a008_81e0cc0c_3d0d810b;
-defparam bootram.RAM1.INIT_39=256'h08757190_3881b8a0_72802e93_81065452_b8a00870_fe3d0d81_e0c00c04_de3f7181;
-defparam bootram.RAM1.INIT_3A=256'hf8d33fff_80da8851_802e8b38_06515271_812a7081_529a3971_53818080_2a710c53;
-defparam bootram.RAM1.INIT_3B=256'h38818080_70802ef2_c0065151_a0087080_3d0d81b8_3d0d0480_71800c84_9e3f7252;
-defparam bootram.RAM1.INIT_3C=256'h70900651_81b8a008_e0cc0c52_2b880781_05227090_3d0d028e_3d0d04ff_0b800c82;
-defparam bootram.RAM1.INIT_3D=256'hba51f7a5_802e8638_54805372_fd3d0d75_833d0d04_81e0cc0c_f338840b_5170802e;
-defparam bootram.RAM1.INIT_3E=256'h33568211_0d778311_0d04fb3d_e638853d_53857327_df3f8113_335252a3_3f721470;
-defparam bootram.RAM1.INIT_3F=256'h029005bb_7c7e6163_04f63d0d_3f873d0d_8c5180ed_535680da_33547033_33558111;
-defparam bootram.RAM2.INIT_00=256'h782d7630_7952ad51_802e8a38_258f3875_59577680_5b5f5d5b_709f2a51_05337030;
-defparam bootram.RAM2.INIT_01=256'h51abe63f_3f775276_0851ffbd_abce3f80_77527651_78548053_94387955_57777726;
-defparam bootram.RAM2.INIT_02=256'h04f73d0d_3f823d0d_3351f68d_0d028b05_0d04803d_782d8c3d_98053351_800880da;
-defparam bootram.RAM2.INIT_03=256'h81ff0656_81d13876_5775802e_81ff0657_58783370_a0ce5c5a_84055208_8c3d7070;
-defparam bootram.RAM2.INIT_04=256'h7580e32e_f024a038_fb387580_80f02e80_33575975_38811970_810680db_75a52e09;
-defparam bootram.RAM2.INIT_05=256'h80f52eac_818b3975_2e80c638_397580e4_9e388195_75802e81_e3248a38_b9387580;
-defparam bootram.RAM2.INIT_06=256'h19831233_ec397784_2eba3880_397580f8_db3880f5_80f32e80_248b3875_387580f5;
-defparam bootram.RAM2.INIT_07=256'h39778419_54805390_8055a0ce_08525956_77841971_2d80da39_52755179_52595680;
-defparam bootram.RAM2.INIT_08=256'h54805390_8055a0ce_08525956_77841971_8a529239_ce548153_568055a0_71085259;
-defparam bootram.RAM2.INIT_09=256'h81055833_80527670_802e8e38_76335675_08595956_77841971_d03f9e39_527551fd;
-defparam bootram.RAM2.INIT_0A=256'h0d81a090_0c04803d_0b81a094_3d0d0481_0b800c8b_fea33980_39811959_51792dec;
-defparam bootram.RAM2.INIT_0B=256'h7b8c8006_7980ff06_02970533_04fd3d0d_38823d0d_515170f1_70810651_0870882a;
-defparam bootram.RAM2.INIT_0C=256'h900c7180_0c7281a0_7781a080_81a0980c_83ffff06_54d03f76_80075553_077080c0;
-defparam bootram.RAM2.INIT_0D=256'h04fc3d0d_0c853d0d_08517080_3f81a080_8938ffaa_5173802e_a0900c73_c2800781;
-defparam bootram.RAM2.INIT_0E=256'h902a5170_51ee3971_81155553_70227305_38721015_7274278f_55558053_76787a54;
-defparam bootram.RAM2.INIT_0F=256'h755280e3_3d0d8653_3d0d04fd_71800c86_0552ec39_0672902a_7183ffff_802e8d38;
-defparam bootram.RAM2.INIT_10=256'h0c8812ff_89518072_80e3fc52_04ff3d0d_54853d0d_80e3f40c_3f767008_ec51adb6;
-defparam bootram.RAM2.INIT_11=256'h22547274_f8525270_800b80e3_96052253_fd3d0d02_833d0d04_8025f338_12525270;
-defparam bootram.RAM2.INIT_12=256'h7183ffff_3d0d787a_3d0d04fa_70800c85_ee388051_52897225_12881252_2e8e3881;
-defparam bootram.RAM2.INIT_13=256'hf8555555_fc0b80e3_800880e3_050cad39_76800884_802e8938_c73f8008_06535856;
-defparam bootram.RAM2.INIT_14=256'h7684140c_3f757323_eb389ac6_55897525_15881454_2e8f3881_55527180_73088815;
-defparam bootram.RAM2.INIT_15=256'h52913ddc_923d8805_853f7353_055254ac_53923dd6_7054933d_f13d0d86_883d0d04;
-defparam bootram.RAM2.INIT_16=256'h0b8c3d23_a6052380_80028405_0b8b3d23_23818a80_8405a205_3f908002_0551abf6;
-defparam bootram.RAM2.INIT_17=256'h538a5291_5d665e80_ae052368_80028405_0b8d3d23_2380c091_8405aa05_81808002;
-defparam bootram.RAM2.INIT_18=256'h0523800b_028405ba_23963d22_3d22903d_ae052398_08028405_fdb73f80_3de40551;
-defparam bootram.RAM2.INIT_19=256'h3f913d0d_05519ca5_2981e684_526980c0_913dd405_0523ac53_028405be_913d2380;
-defparam bootram.RAM2.INIT_1A=256'hec529a3d_865380e3_51aae33f_9a3df205_539b3d52_973d2386_805b800b_04e83d0d;
-defparam bootram.RAM2.INIT_1B=256'h0b9b3dc4_08585a80_3f800880_0523f7f7_840580e2_f2052202_d53f0280_f80551aa;
-defparam bootram.RAM2.INIT_1C=256'h088305fc_085fa33d_6e5ea13d_845c905d_3d084659_3d0845a3_436e44a1_1143f005;
-defparam bootram.RAM2.INIT_1D=256'h760c7508_27843873_5a557375_71315156_7c319080_08701a78_56845875_06408c3d;
-defparam bootram.RAM2.INIT_1E=256'heffb3f75_80dab451_802e8838_83065473_38941608_0654738c_9a387383_5473802e;
-defparam bootram.RAM2.INIT_1F=256'h78bf2684_25ffac38_59577780_0817ff19_70840557_9af73f75_08527651_08539416;
-defparam bootram.RAM2.INIT_20=256'h237f1f94_800b943d_4040818a_3d0d6b6e_3d0d04ea_f6fd3f9a_78822a51_3880c059;
-defparam bootram.RAM2.INIT_21=256'h80075a79_236980c0_0580ce05_80800284_953d2381_0523800b_840580ca_055a7902;
-defparam bootram.RAM2.INIT_22=256'he03f8008_70525cfa_8a52933d_68478053_e3f40846_d2052380_02840580_963d2380;
-defparam bootram.RAM2.INIT_23=256'h5a799238_0881ff06_8ac83f80_70535c5e_7053983d_0523913d_840580d2_095a7902;
-defparam bootram.RAM2.INIT_24=256'h557b5490_6b575d94_6d596058_39027f5a_edea3fa9_51f6cb3f_f7d73f7a_80dae051;
-defparam bootram.RAM2.INIT_25=256'h04f73d0d_3f983d0d_ef38fd89_5c867c26_7b34811c_5b5b7933_7b1d7c1f_8053805c;
-defparam bootram.RAM2.INIT_26=256'h05a60523_23800284_57768b3d_05238818_028405a2_238d3d22_05228a3d_7f5802ae;
-defparam bootram.RAM2.INIT_27=256'h3d239080_0d810b8e_0d04ee3d_9e3f8b3d_527d51fe_f8055391_88548b3d_77567e55;
-defparam bootram.RAM2.INIT_28=256'h86538008_23eab13f_8405b605_05348102_028405b5_8f3d3484_0523860b_028405b2;
-defparam bootram.RAM2.INIT_29=256'h52943df6_3f865380_0551a782_52943df2_84538008_3feb803f_0551a792_52943dec;
-defparam bootram.RAM2.INIT_2A=256'h54908653_943de405_80569c55_80588057_025c8059_80080843_3feae43f_0551a88f;
-defparam bootram.RAM2.INIT_2B=256'h3d0daa3d_3d0d04d9_fbcb3f94_7b26ef38_811b5b86_1b337a34_5a80daac_805b7a1c;
-defparam bootram.RAM2.INIT_2C=256'h9b268d38_055b5b79_088429f2_901dac3d_06829d38_862e0981_5f5d7d90_088e1122;
-defparam bootram.RAM2.INIT_2D=256'h7990802e_821b225a_0686e238_812e0981_7a225a79_3f86ee39_9051f5b5_795280db;
-defparam bootram.RAM2.INIT_2E=256'h810686b9_79812e09_861b225a_0686c638_842e0981_225a798c_d438841b_09810686;
-defparam bootram.RAM2.INIT_2F=256'hffa80551_f452a93d_845380e3_3f800843_525f87fd_3fa81d70_52408885_389e1d70;
-defparam bootram.RAM2.INIT_30=256'h3d23821b_3f7a22a1_7951a5a2_80e3ec52_3d5a8653_868f38a7_085c8008_a4c43f80;
-defparam bootram.RAM2.INIT_31=256'h81820523_82028405_81810534_33028405_3d34851b_841b33a2_80fe0523_22028405;
-defparam bootram.RAM2.INIT_32=256'h8e055b86_e13f0281_05525aa4_53aa3dea_8470547f_51a4ef3f_a93de405_86537952;
-defparam bootram.RAM2.INIT_33=256'h7e51a4ba_86537a52_3f9e3d5f_0551a4c6_52a93df4_3f79537f_7a51a4d2_53981d52;
-defparam bootram.RAM2.INIT_34=256'h7b34811c_5b5b7933_7b1d7f1d_05547d53_55a93ddc_7c575d9c_7c597c58_3f027c5a;
-defparam bootram.RAM2.INIT_35=256'h2a435b5b_7022708c_e438901d_09810684_7d90802e_3f84ee39_ef38f999_5c867c26;
-defparam bootram.RAM2.INIT_36=256'h2280ffff_c038861b_09810684_5a79852e_708f0651_3879882a_810684d1_60842e09;
-defparam bootram.RAM2.INIT_37=256'h1c625580_815e7e90_80088338_51a2d33f_ac52821d_865380da_b4387e5e_065f7e84;
-defparam bootram.RAM2.INIT_38=256'h9c1d5184_38881d52_802e8481_7d87387b_8338815c_bd3f8008_535b5ca2_e3f45470;
-defparam bootram.RAM2.INIT_39=256'h8c1b087a_0683de38_912e0981_81bb387f_407f812e_ec11405d_33821c22_b83f891b;
-defparam bootram.RAM2.INIT_3A=256'h39ac1de4_843f83bd_dbb051f2_537d5280_2e8f3879_42407d7a_11225d5d_08a41f84;
-defparam bootram.RAM2.INIT_3B=256'h3d993d5f_237f499a_7a22993d_2e83a638_42800880_c33f8008_535d5df5_1d821d22;
-defparam bootram.RAM2.INIT_3C=256'h60478853_22973d23_a53f821b_527f51a2_40885379_b13f9c3d_527951a2_5a88537d;
-defparam bootram.RAM2.INIT_3D=256'h5c7b1d7c_7e843d5e_7b567c55_51a2873f_5379527d_a2903f88_05527951_a93dffb4;
-defparam bootram.RAM2.INIT_3E=256'h1b5b887b_051c3481_79330284_5b7f1b5a_26ef3880_1c5c887c_337b3481_1f5b5b79;
-defparam bootram.RAM2.INIT_3F=256'h7d882e81_832e8a38_405b427d_a41e7033_398c1b08_792d82ad_8405085a_26ef3861;
-defparam bootram.RAM3.INIT_00=256'h5c79912e_12335c5e_80c01e89_a238ac1d_09810681_5a79832e_39811a33_bb388295;
-defparam bootram.RAM3.INIT_01=256'h9b3d2379_085a7c22_fe388c1c_08802e80_80084180_51f4813f_f4387c22_09810681;
-defparam bootram.RAM3.INIT_02=256'h901c085a_51a0df3f_537d527f_963d4088_51a0eb3f_537a527d_3d5c5e88_4b983d9b;
-defparam bootram.RAM3.INIT_03=256'h3f7e567e_7d51a0be_88537a52_51a0c73f_cc05527a_8853a93d_3d23794d_821d229d;
-defparam bootram.RAM3.INIT_04=256'h5a793302_805b7f1b_7c26ef38_811c5c88_79337b34_7c1f5b5b_5e5c7b1d_557e843d;
-defparam bootram.RAM3.INIT_05=256'hac1de41d_3f80de39_e951e5ad_5a792d80_60840508_7b26ef38_811b5b88_84051c34;
-defparam bootram.RAM3.INIT_06=256'h861a2202_22963d23_0523841a_840580ce_05347e02_840580cd_3d347e02_5d5d7e95;
-defparam bootram.RAM3.INIT_07=256'hc03f8008_527c51f1_537b812a_cc3f8008_70525bf1_6052943d_05237e53_840580d2;
-defparam bootram.RAM3.INIT_08=256'h04fc3d0d_3fa93d0d_6151f5f7_7a537f52_7c557d54_05237b56_840580ce_095a7902;
-defparam bootram.RAM3.INIT_09=256'h70752e09_8c135351_56517108_80e4d054_38767008_727427a4_c8085553_800b80e4;
-defparam bootram.RAM3.INIT_0A=256'h77797153_04fb3d0d_0c863d0d_ff517080_7326e738_81135373_72518b39_81068538;
-defparam bootram.RAM3.INIT_0B=256'h3980e4cc_e4c80c8e_38811480_73872689_e4c80854_25ba3880_3f800880_5755ffb9;
-defparam bootram.RAM3.INIT_0C=256'h5280e4d4_54865375_d0120c51_760880e4_1470822b_0c547310_0680e4cc_08811187;
-defparam bootram.RAM3.INIT_0D=256'h0d04fd3d_813f873d_d405519e_842980e4_53755273_08055486_80081080_14519439;
-defparam bootram.RAM3.INIT_0E=256'hd4055276_842980e4_54865373_10800805_99388008_73800824_d83f8054_0d7551fe;
-defparam bootram.RAM3.INIT_0F=256'h07821433_2b71902b_12337198_75703381_04fd3d0d_0c853d0d_81547380_519dd73f;
-defparam bootram.RAM3.INIT_10=256'he5b02256_0d7d7f80_0d04f93d_5452853d_52535456_7107800c_07831633_70882b72;
-defparam bootram.RAM3.INIT_11=256'h14709029_38739029_832680d3_52565473_22707231_ff068b3d_387383ff_595776a8;
-defparam bootram.RAM3.INIT_12=256'h26ad3874_57547483_70723157_068d3d22_7383ffff_2380c039_51547674_80e5b405;
-defparam bootram.RAM3.INIT_13=256'h17703353_27913875_80567578_519cc73f_80e5b405_52739029_88538a3d_90291554;
-defparam bootram.RAM3.INIT_14=256'h80e5b454_b023800b_052280e5_3d0d029a_3d0d04fc_56ec3989_b23f8116_547451e3;
-defparam bootram.RAM3.INIT_15=256'h3f811482_0551ef9b_e5b02274_b4965280_828c140c_140c800b_800b8288_54807323;
-defparam bootram.RAM3.INIT_16=256'h70810651_7c2c8132_b45a5c84_800b80e5_04f43d0d_38863d0d_837427d9_90145454;
-defparam bootram.RAM3.INIT_17=256'h3f8008ff_7b51e2f7_1a88055b_80d63878_7981ff26_1a085b5d_38758288_567581be;
-defparam bootram.RAM3.INIT_18=256'h59515858_25075351_80257180_32703072_7030728d_06708a32_800881ff_2e80c538;
-defparam bootram.RAM3.INIT_19=256'h1a0c811a_800b828c_82881a0c_19088105_5d348288_7b708105_38815d77_76802e83;
-defparam bootram.RAM3.INIT_1A=256'h1b0c568b_8111828c_828c1908_387c9138_802e80d2_82881908_27ffb138_5a81ff7a;
-defparam bootram.RAM3.INIT_1B=256'h781a5757_5b58771a_800b833d_55881954_82881908_802eab38_78225675_7627bf38;
-defparam bootram.RAM3.INIT_1C=256'h800b828c_82881a0c_a83f800b_7c0551f2_80e5b022_7826ef38_81185888_75337734;
-defparam bootram.RAM3.INIT_1D=256'hc0526851_70545780_3d0d883d_3d0d04ea_fea9388e_5c837c27_82901a5a_1a0c811c;
-defparam bootram.RAM3.INIT_1E=256'h81069438_81aa2e09_2e9d3873_547381ff_17703351_05575574_0284059d_93973f80;
-defparam bootram.RAM3.INIT_1F=256'h5473800c_27d13880_1555be75_548b3981_06853881_992e0981_51547381_74167033;
-defparam bootram.RAM3.INIT_20=256'h5198a73f_dbd45273_55845380_92c73f80_84527951_3d705454_f93d0d86_983d0d04;
-defparam bootram.RAM3.INIT_21=256'h8c8b3f88_04fc3d0d_81e0940c_0d04810b_800c893d_38815574_09810683_8008752e;
-defparam bootram.RAM3.INIT_22=256'h2a708106_b408708d_ec3f81b8_3f805187_5255e88d_5380dbd8_81ff0670_f63f8008;
-defparam bootram.RAM3.INIT_23=256'hb63f8008_800a51fe_dee33f98_80dca851_3974b538_f0518183_883880db_51515473;
-defparam bootram.RAM3.INIT_24=256'h3f80dd8c_0a5183f7_823f9880_82ac51e3_5187b23f_decf3f81_80dcd451_802e9a38;
-defparam bootram.RAM3.INIT_25=256'h80ffff52_83808053_51dea23f_3880ddb4_08802ebb_feda3f80_8c800a51_51deb63f;
-defparam bootram.RAM3.INIT_26=256'hfc3f82ac_de8451dd_fedc3f80_51e2c43f_8c3f82ac_dde051de_91933f80_8c800a51;
-defparam bootram.RAM3.INIT_27=256'hfd3d0d75_edf40c04_0d047180_e83f863d_dec051dd_3f883980_805183ab_51e2b43f;
-defparam bootram.RAM3.INIT_28=256'h80edf408_51dc8c3f_3f725272_8c51e6c9_735280df_3880c053_87e82e84_54a05373;
-defparam bootram.RAM3.INIT_29=256'h51dbe83f_80c05280_51dbf03f_0da05280_0d04fe3d_722d853d_85387351_5372802e;
-defparam bootram.RAM3.INIT_2A=256'h8008862a_a53fff0b_0d9a5187_0d04fc3d_722d843d_85388051_5372802e_80edf408;
-defparam bootram.RAM3.INIT_2B=256'h802e9b38_e4547182_06535580_80088680_ec38820b_71802e80_53548155_70810651;
-defparam bootram.RAM3.INIT_2C=256'h86e03f80_ff548451_802e8338_e8547184_388a3987_71802e8e_8a388a54_71828024;
-defparam bootram.RAM3.INIT_2D=256'hee800c80_11337080_0780e084_70830672_80088a2c_882a8c06_86d83f71_08528551;
-defparam bootram.RAM3.INIT_2E=256'hf8082e98_3f7480ed_5252dc81_e2fc1108_2b8c0680_e83f7182_515452db_dfc45553;
-defparam bootram.RAM3.INIT_2F=256'h81069638_74822e09_b93f9e39_06a338fe_812e0981_2ea63874_f80c7482_387480ed;
-defparam bootram.RAM3.INIT_30=256'h0d04fd3d_e53f863d_3f995185_7351fde8_0cfe9f3f_7380edfc_082e8e38_7380edfc;
-defparam bootram.RAM3.INIT_31=256'h52985185_85c43f8d_fc0c9951_ff0b80ed_80edf80c_ba3f800b_80085185_0dd8a93f;
-defparam bootram.RAM3.INIT_32=256'h07f49f06_80089080_5185a73f_e0e93f84_d2528451_85e53fba_80529c51_ee3f81ae;
-defparam bootram.RAM3.INIT_33=256'he3df3f80_80dfdc51_08537352_2e8d3880_3f738008_84518592_5185c83f_70535484;
-defparam bootram.RAM3.INIT_34=256'h05538052_54873dfc_fb3d0d82_3d0d0404_85a13f85_07528051_80088480_5184fb3f;
-defparam bootram.RAM3.INIT_35=256'h12085859_d73d0884_d53d0880_b23d0d80_3d0d04ff_22800c87_c43f863d_80d05183;
-defparam bootram.RAM3.INIT_36=256'h2681cc38_16567596_d639ff9f_e38b3f81_80e09451_53829452_26903877_57778293;
-defparam bootram.RAM3.INIT_37=256'h800b81e1_81e1800c_5e890a0b_3f800808_c15cd7bb_75080480_e0e00556_75842980;
-defparam bootram.RAM3.INIT_38=256'h0b81e4d0_e2c80c80_0c800b81_0b81e2c4_e2c00c80_890a0b81_81e1880c_840c800b;
-defparam bootram.RAM3.INIT_39=256'hffff065e_3f800883_f839fedc_80c65c80_3f80085f_085e8ca2_8c9e3f80_0c818a39;
-defparam bootram.RAM3.INIT_3A=256'heeac518a_80d33980_3f80c55c_ac5189d1_085280ee_08538c17_e8399017_80d65c80;
-defparam bootram.RAM3.INIT_3B=256'h08528c17_17539017_5cb73994_bc3980c2_3880c45c_75802e86_81ff0656_963f8008;
-defparam bootram.RAM3.INIT_3C=256'h80d25c8d_518bbe3f_528c1708_53901708_3dfe8005_a43980d0_3f80d75c_085188b8;
-defparam bootram.RAM3.INIT_3D=256'h58771980_0b833d5a_ec055480_80d03dfd_5c829455_3f8339a0_8051fdeb_3980d35c;
-defparam bootram.RAM3.INIT_3E=256'h0d04803d_3f80d03d_8251e9e5_ec388380_58887826_77348118_57577533_d23d7905;
-defparam bootram.RAM3.INIT_3F=256'h54807425_74ff1656_5a575758_7a7c7f7f_3ff83d0d_ff5182f3_51d7ca3f_0d80e1bc;
-defparam bootram.RAM4.INIT_00=256'h05527781_538a3dfc_a1053482_33028405_70810558_8a3d3476_17575473_b7387581;
-defparam bootram.RAM4.INIT_01=256'h0c8a3d0d_81547380_8538c139_3f73802e_8a51dbe7_81ff0654_b93f8008_ff0651da;
-defparam bootram.RAM4.INIT_02=256'h81f75280_3dfc0553_34815488_5675883d_748338dc_5580de56_02a30533_04fa3d0d;
-defparam bootram.RAM4.INIT_03=256'h02a70533_3dfc0552_34815389_0533893d_7c5702ab_04f93d0d_3f883d0d_d051ff89;
-defparam bootram.RAM4.INIT_04=256'h7551d89c_76537b52_77259738_2e9e3880_56547380_81ff0670_d93f8008_705256d9;
-defparam bootram.RAM4.INIT_05=256'h883dfc05_3d0d8154_3d0d04fa_74800c89_83388155_5473802e_ff067056_3f800881;
-defparam bootram.RAM4.INIT_06=256'h75800c88_83388156_2e098106_567480de_883d3356_a03f800b_80d051ff_5381f752;
-defparam bootram.RAM4.INIT_07=256'h0c04803d_0b81c0b0_ac0c89b0_a60b81c0_81c0800c_0c80eb0b_0b81c094_3d0d0499;
-defparam bootram.RAM4.INIT_08=256'h70810651_0870812a_0c81c0a4_0b81c0a0_980c5182_810781c0_be800670_0d72882b;
-defparam bootram.RAM4.INIT_09=256'hc0980c51_70810781_2bbe8006_3d0d7288_3d0d0480_08800c82_3881c0a8_515170f1;
-defparam bootram.RAM4.INIT_0A=256'h3d0d04ff_70f13882_06515151_812a7081_c0a40870_c0a00c81_0c840b81_7381c09c;
-defparam bootram.RAM4.INIT_0B=256'h71802e86_72830652_52718a38_38758306_57577191_83065555_787a7c72_39fa3d0d;
-defparam bootram.RAM4.INIT_0C=256'h52545281_7008720c_77117712_3873822b_73752794_2a725555_f33f7282_38815188;
-defparam bootram.RAM4.INIT_0D=256'ha83f728f_515353d3_c8113354_8f0680e1_70842a70_fe3d0d74_883d0d04_1454e939;
-defparam bootram.RAM4.INIT_0E=256'h51515170_2a708106_90087088_3d0d82e0_3d0d0480_d39b3f84_11335253_0680e1c8;
-defparam bootram.RAM4.INIT_0F=256'h82e09008_80075353_060780c0_067a8c80_337880ff_0d029305_0d04fe3d_f138823d;
-defparam bootram.RAM4.INIT_10=256'h980c7182_ff0682e0_900c7581_0c7182e0_7682e080_5170f138_81065151_70882a70;
-defparam bootram.RAM4.INIT_11=256'h3882e080_515170f1_70810651_0870882a_3882e090_72802e96_900c7251_800782e0;
-defparam bootram.RAM4.INIT_12=256'h51ff873f_53805280_55885480_940c8880_810b82e0_04fc3d0d_0c843d0d_08517080;
-defparam bootram.RAM4.INIT_13=256'h0c863d0d_81ff0680_f13f8008_528151fe_8a805381_80559054_fc3d0d88_863d0d04;
-defparam bootram.RAM4.INIT_14=256'h08813281_0dca3f80_0d04803d_d53f863d_528051fe_54865381_88805588_04fc3d0d;
-defparam bootram.RAM4.INIT_15=256'h3d0d7756_3d0d04fb_2ef43882_06517080_800881ff_3d0deb3f_3d0d0480_06800c82;
-defparam bootram.RAM4.INIT_16=256'h81528051_9b0a0753_fe9b0a06_55a05475_b43f8880_38dd3fff_8008269b_858c3f75;
-defparam bootram.RAM4.INIT_17=256'hff2681b4_80557381_11565757_cb3d08ff_c93d0880_ba3d0d80_3d0d04ff_fe843f87;
-defparam bootram.RAM4.INIT_18=256'h755380cb_548cb83f_883d7052_5381ff52_a7388280_80082681_84c83f73_38751754;
-defparam bootram.RAM4.INIT_19=256'h0c76fec0_0b82e090_980c8880_3f7482e0_d43ffd9f_fefd3ffe_518b933f_3d085273;
-defparam bootram.RAM4.INIT_1A=256'h900cfcef_a00b82e0_e0900c8a_88a00b82_82e0980c_800c810b_0a0782e0_0a0680c0;
-defparam bootram.RAM4.INIT_1B=256'h88157008_880c54fe_700882e0_54fe8415_82e08c0c_80157008_558f56fe_3f80c83d;
-defparam bootram.RAM4.INIT_1C=256'h0cfcb03f_0b82e090_900c8a80_800b82e0_800c5488_700882e0_54fe8c15_82e0840c;
-defparam bootram.RAM4.INIT_1D=256'hf93d0d79_c83d0d04_74800c80_980c8155_800b82e0_25ffbc38_56567580_ff169016;
-defparam bootram.RAM4.INIT_1E=256'h7581ff06_2e80c338_81577480_2680cb38_57738008_83843f80_575a5656_7b7d7212;
-defparam bootram.RAM4.INIT_1F=256'h3f731674_7551fdeb_77537352_83387654_57767527_74317555_a2388280_5473802e;
-defparam bootram.RAM4.INIT_20=256'h81577680_39fd8c3f_828054dc_7527e138_74548280_802e8e38_57595674_19767631;
-defparam bootram.RAM4.INIT_21=256'h27903880_3f800874_13548296_2e8d3873_54557380_76787a56_04fc3d0d_0c893d0d;
-defparam bootram.RAM4.INIT_22=256'h81e63f80_16565152_707406ff_3f800830_a63981f4_0c80750c_800b8416_0b88160c;
-defparam bootram.RAM4.INIT_23=256'hfc983f80_3d0d7554_3d0d04fd_fcc93f86_160c7151_160c7188_0c740684_08307276;
-defparam bootram.RAM4.INIT_24=256'h08800805_ab3f8814_2e943881_08841508_81538814_802e9f38_70545271_0881ff06;
-defparam bootram.RAM4.INIT_25=256'h53815281_5481f90a_888055a0_04fc3d0d_0c853d0d_80537280_51fc943f_7088160c;
-defparam bootram.RAM4.INIT_26=256'h3f800888_74bf38d5_ee840855_fb3d0d80_863d0d04_0a06800c_8008fe80_51faa33f;
-defparam bootram.RAM4.INIT_27=256'h38815573_73a02e83_54d6e63f_d8545851_715580e1_ff067056_06800881_2a7081ff;
-defparam bootram.RAM4.INIT_28=256'h08ea1155_0c80ee84_7580ee84_f0519739_873880e1_5473802e_38748106_80c02e90;
-defparam bootram.RAM4.INIT_29=256'h80e2f605_973f8008_3d0d04ff_74800c87_3ff5af3f_9051cd85_8b3880e2_55827427;
-defparam bootram.RAM4.INIT_2A=256'h7d56f8ef_04f63d0d_082b800c_3f810b80_0c04ff80_80082b80_f23f810b_33800c04;
-defparam bootram.RAM4.INIT_2B=256'h0b82e098_e0800c81_7c882b82_82e0840c_900c8b0b_800b82e0_e0980c88_3f800b82;
-defparam bootram.RAM4.INIT_2C=256'h88800b82_2780d338_80547376_be3f7e55_e0900cf8_8aa80b82_82e0900c_0c88a80b;
-defparam bootram.RAM4.INIT_2D=256'h82e08008_e084085a_88085982_085882e0_3f82e08c_900cf8a3_800b82e0_e0900c8a;
-defparam bootram.RAM4.INIT_2E=256'h33757081_71175170_73279138_53805271_27833870_90537073_75315257_5b883d76;
-defparam bootram.RAM4.INIT_2F=256'h51f6e03f_803d0d72_8c3d0d04_82e0980c_a939800b_721454ff_1252ec39_05573481;
-defparam bootram.RAM4.INIT_30=256'h800c5485_3f800870_085182de_8c088805_8c050852_80538c08_0cfd3d0d_8c08028c;
-defparam bootram.RAM4.INIT_31=256'hb93f8008_05085182_528c0888_088c0508_0d81538c_8c0cfd3d_048c0802_3d0d8c0c;
-defparam bootram.RAM4.INIT_32=256'h05088025_0c8c0888_8c08fc05_3d0d800b_028c0cf9_0c048c08_853d0d8c_70800c54;
-defparam bootram.RAM4.INIT_33=256'h0b8c08f4_08883881_8c08fc05_08f4050c_0c800b8c_8c088805_88050830_ab388c08;
-defparam bootram.RAM4.INIT_34=256'h088c050c_0508308c_388c088c_088025ab_8c088c05_08fc050c_f405088c_050c8c08;
-defparam bootram.RAM4.INIT_35=256'hfc050c80_05088c08_0c8c08f0_8c08f005_8838810b_08fc0508_f0050c8c_800b8c08;
-defparam bootram.RAM4.INIT_36=256'h0508802e_548c08fc_08f8050c_8008708c_5181a73f_08880508_0508528c_538c088c;
-defparam bootram.RAM4.INIT_37=256'h8c08028c_0d8c0c04_0c54893d_05087080_0c8c08f8_8c08f805_f8050830_8c388c08;
-defparam bootram.RAM4.INIT_38=256'h88050c81_08308c08_8c088805_80259338_08880508_fc050c8c_800b8c08_0cfb3d0d;
-defparam bootram.RAM4.INIT_39=256'h8c088c05_050c8153_308c088c_088c0508_258c388c_8c050880_050c8c08_0b8c08fc;
-defparam bootram.RAM4.INIT_3A=256'h8c08f805_802e8c38_08fc0508_050c548c_708c08f8_ad3f8008_88050851_08528c08;
-defparam bootram.RAM4.INIT_3B=256'h3d0d810b_028c0cfd_0c048c08_873d0d8c_70800c54_08f80508_f8050c8c_08308c08;
-defparam bootram.RAM4.INIT_3C=256'h0508802e_388c08fc_050827ac_088c0888_8c088c05_08f8050c_0c800b8c_8c08fc05;
-defparam bootram.RAM4.INIT_3D=256'h108c08fc_08fc0508_8c050c8c_08108c08_8c088c05_08249938_8c088c05_a338800b;
-defparam bootram.RAM4.INIT_3E=256'h08880508_26a1388c_08880508_8c05088c_c9388c08_08802e80_8c08fc05_050cc939;
-defparam bootram.RAM4.INIT_3F=256'h08fc0508_f8050c8c_08078c08_8c08fc05_08f80508_88050c8c_08318c08_8c088c05;
-defparam bootram.RAM5.INIT_00=256'h2e8f388c_90050880_af398c08_8c050cff_812a8c08_088c0508_fc050c8c_812a8c08;
-defparam bootram.RAM5.INIT_01=256'h0508800c_518c08f4_08f4050c_0508708c_398c08f8_050c518d_708c08f4_08880508;
-defparam bootram.RAM5.INIT_02=256'h2eb038ff_06517080_74740783_72278c38_56565283_0d787779_0c04fc3d_853d0d8c;
-defparam bootram.RAM5.INIT_03=256'h555571ff_15ff1454_38811581_098106bd_5372712e_33743352_2ea03874_125271ff;
-defparam bootram.RAM5.INIT_04=256'h84118414_81068f38_73082e09_54517008_0d047474_800c863d_e238800b_2e098106;
-defparam bootram.RAM5.INIT_05=256'h0d767079_0d04fc3d_800c863d_39727131_5555ffaf_e9387073_51718326_fc145454;
-defparam bootram.RAM5.INIT_06=256'h38727081_71ff2e98_38ff1252_70802ea7_07830651_8c387275_558f7227_7b555555;
-defparam bootram.RAM5.INIT_07=256'h51727084_3d0d0474_74800c86_8106ea38_71ff2e09_34ff1252_70810556_05543374;
-defparam bootram.RAM5.INIT_08=256'h70840553_05540871_0c727084_70840553_05540871_0c727084_70840553_05540871;
-defparam bootram.RAM5.INIT_09=256'h84055408_95387270_38837227_718f26c9_0cf01252_70840553_05540871_0c727084;
-defparam bootram.RAM5.INIT_0A=256'h9f053357_71028c05_3d0d7679_ff8339fc_ed387054_52718326_530cfc12_71708405;
-defparam bootram.RAM5.INIT_0B=256'h81055534_38737370_71ff2e93_38ff1252_70802ea2_74830651_72278a38_55535583;
-defparam bootram.RAM5.INIT_0C=256'h07515451_7071902b_882b7507_0d047474_800c863d_06ef3874_ff2e0981_ff125271;
-defparam bootram.RAM5.INIT_0D=256'h70840553_530c7271_71708405_05530c72_72717084_8405530c_38727170_8f7227a5;
-defparam bootram.RAM5.INIT_0E=256'h387053ff_718326f2_0cfc1252_70840553_90387271_38837227_718f26dd_0cf01252;
-defparam bootram.RAM5.INIT_0F=256'h80d438ff_5170802e_74078306_80d93871_5272802e_70545555_0d787a7c_9039fa3d;
-defparam bootram.RAM5.INIT_10=256'h81ff0651_81873870_3872802e_098106a9_5174712e_33743356_2eb13871_135372ff;
-defparam bootram.RAM5.INIT_11=256'h517081ff_33743356_06d13871_ff2e0981_55555272_8115ff15_fc388112_70802e80;
-defparam bootram.RAM5.INIT_12=256'h0874082e_27883871_57558373_0d047174_800c883d_51525270_06717131_067581ff;
-defparam bootram.RAM5.INIT_13=256'hf8848281_ff120670_09f7fbfd_38740870_72802eb1_39fc1353_5552ff97_88387476;
-defparam bootram.RAM5.INIT_14=256'h5552fedf_d0387476_0876082e_27d03874_57558373_84158417_51709a38_80065151;
-defparam bootram.RAM5.INIT_15=256'h880cffb3_387380ee_72812e9e_d0085454_800b80e2_04fd3d0d_0c883d0d_39800b80;
-defparam bootram.RAM5.INIT_16=256'hb3823fff_ee880cff_a33f7280_800851f6_ffbac43f_90528151_bb3f80e3_9f3fffb2;
-defparam bootram.RAM5.INIT_17=256'h0bfc0570_0d80e398_ff39ff3d_f6863f00_3f800851_51ffbaa7_e3905281_b29e3f80;
-defparam bootram.RAM5.INIT_18=256'h04ffb3ad_833d0d04_8106f138_70ff2e09_70085252_702dfc12_ff2e9138_08525270;
-defparam bootram.RAM5.INIT_19=256'h636b6574_6c207061_6e74726f_6e20636f_6f722069_21457272_00000040_3f040000;
-defparam bootram.RAM5.INIT_1A=256'h6c697479_74696269_6f6d7061_65642063_70656374_3a204578_646c6572_2068616e;
-defparam bootram.RAM5.INIT_1B=256'h6f722069_21457272_25640a00_676f7420_62757420_25642c20_62657220_206e756d;
-defparam bootram.RAM5.INIT_1C=256'h70656374_3a204578_646c6572_2068616e_636b6574_6c207061_6e74726f_6e20636f;
-defparam bootram.RAM5.INIT_1D=256'h74202564_7420676f_2c206275_68202564_656e6774_6164206c_61796c6f_65642070;
-defparam bootram.RAM5.INIT_1E=256'h203d2025_70656564_643a2073_616e6765_6b206368_206c696e_0a657468_0a000000;
-defparam bootram.RAM5.INIT_1F=256'h720a0000_6f616465_6f6f746c_44502062_31302055_50204e32_0a555352_640a0000;
-defparam bootram.RAM5.INIT_20=256'h640a0000_723a2025_756d6265_7479206e_62696c69_70617469_20636f6d_46504741;
-defparam bootram.RAM5.INIT_21=256'h723a2025_756d6265_7479206e_62696c69_70617469_20636f6d_77617265_4669726d;
-defparam bootram.RAM5.INIT_22=256'h7061636b_65727920_65636f76_69702072_476f7420_00000000_61646472_640a0000;
-defparam bootram.RAM5.INIT_23=256'h0000079e_00000774_0000079e_0000079e_000006ee_00000705_00000000_65743a20;
-defparam bootram.RAM5.INIT_24=256'h00000699_0000079e_000006a6_00000722_0000079e_0000079e_0000079e_0000079e;
-defparam bootram.RAM5.INIT_25=256'h20636869_4c4d5331_00000762_00000755_0000074e_00000747_00000742_0000073d;
-defparam bootram.RAM5.INIT_26=256'h70207665_20636869_4c4d5332_0a000000_30782578_6e203d20_7273696f_70207665;
-defparam bootram.RAM5.INIT_27=256'h15290a94_3fff0000_0050c285_c0a80a02_0a000000_30782578_6e203d20_7273696f;
-defparam bootram.RAM5.INIT_28=256'h34353637_30313233_2e256400_642e2564_25642e25_45000000_01c300e2_054a0387;
-defparam bootram.RAM5.INIT_29=256'h3a206261_5f706b74_73656e64_ffff0000_ffffffff_00000000_43444546_38394142;
-defparam bootram.RAM5.INIT_2A=256'h66000000_72206275_6e642f6f_656e2061_6f66206c_656e7420_69676e6d_6420616c;
-defparam bootram.RAM5.INIT_2B=256'h63686520_74206361_6f206869_65642074_6661696c_6f6e3a20_636f6d6d_6e65745f;
-defparam bootram.RAM5.INIT_2C=256'h20776569_6172703a_646c655f_0a68616e_00000000_666f7220_696e6720_6c6f6f6b;
-defparam bootram.RAM5.INIT_2D=256'h74656e74_6e736973_696e636f_55445020_0a000000_3d202564_697a6520_72642073;
-defparam bootram.RAM5.INIT_2E=256'h75637469_50726f64_0b0b0b0b_00000000_2025640a_3a202564_67746873_206c656e;
-defparam bootram.RAM5.INIT_2F=256'h50322b20_20555352_74696e67_53746172_640a0000_203d2025_6d616765_6f6e2069;
-defparam bootram.RAM5.INIT_30=256'h69726d77_66652066_67207361_6164696e_2e204c6f_6d6f6465_61666520_696e2073;
-defparam bootram.RAM5.INIT_31=256'h726f6475_69642070_2076616c_20666f72_6b696e67_43686563_00000000_6172652e;
-defparam bootram.RAM5.INIT_32=256'h6f647563_64207072_56616c69_2e2e2e00_6d616765_47412069_6e204650_6374696f;
-defparam bootram.RAM5.INIT_33=256'h7074696e_7474656d_642e2041_666f756e_61676520_4120696d_20465047_74696f6e;
-defparam bootram.RAM5.INIT_34=256'h696f6e20_64756374_2070726f_616c6964_4e6f2076_742e0000_20626f6f_6720746f;
-defparam bootram.RAM5.INIT_35=256'h6f647563_64207072_56616c69_2e0a0000_6f756e64_67652066_20696d61_46504741;
-defparam bootram.RAM5.INIT_36=256'h2e2e2e00_64696e67_204c6f61_756e642e_6520666f_6d776172_20666972_74696f6e;
-defparam bootram.RAM5.INIT_37=256'h6d616765_6e672069_61727469_2e205374_64696e67_206c6f61_73686564_46696e69;
-defparam bootram.RAM5.INIT_38=256'h70726f67_61696e20_6f6d206d_6e206672_65747572_523a2052_4552524f_2e000000;
-defparam bootram.RAM5.INIT_39=256'h6e210000_61707065_65722068_206e6576_6f756c64_73207368_20546869_72616d21;
-defparam bootram.RAM5.INIT_3A=256'h20666f75_77617265_6669726d_696f6e20_64756374_2070726f_616c6964_4e6f2076;
-defparam bootram.RAM5.INIT_3B=256'h2d696e20_75696c74_746f2062_75676820_7468726f_696e6720_46616c6c_6e642e20;
-defparam bootram.RAM5.INIT_3C=256'h00000000_2025640a_7420746f_64207365_53706565_2e000000_77617265_6669726d;
-defparam bootram.RAM5.INIT_3D=256'h45545249_53594d4d_58000000_57455f52_58000000_57455f54_00000000_4e4f4e45;
-defparam bootram.RAM5.INIT_3E=256'h5048595f_6c3a2000_6e74726f_7720636f_20666c6f_726e6574_65746865_43000000;
-defparam bootram.RAM5.INIT_3F=256'h20307825_20676f74_7825782c_74652030_2077726f_4144563a_4e45475f_4155544f;
-defparam bootram.RAM6.INIT_00=256'h6e207570_6f722069_21457272_00030203_00000001_00030003_00000000_780a0000;
-defparam bootram.RAM6.INIT_01=256'h64207061_65637465_20457870_6c65723a_68616e64_6b657420_20706163_64617465;
-defparam bootram.RAM6.INIT_02=256'h00000000_2025640a_20676f74_20627574_2025642c_6e677468_64206c65_796c6f61;
-defparam bootram.RAM6.INIT_03=256'h00001fab_00001fab_00001f24_00001f46_00001f5b_00001fab_00001fab_00001eeb;
-defparam bootram.RAM6.INIT_04=256'h00001fab_00001fab_00001fab_00001fab_00001fab_00001fab_00001fab_00001fab;
-defparam bootram.RAM6.INIT_05=256'h0a0a6162_00001f77_00001f36_00001fab_00001fab_00001fa1_00001f8a_00001fab;
-defparam bootram.RAM6.INIT_06=256'h73682074_0a666c61_43444546_38394142_34353637_30313233_00000000_6f72740a;
-defparam bootram.RAM6.INIT_07=256'h20747970_6c617368_6e672066_0a57726f_25640a00_697a653d_25642073_7970653d;
-defparam bootram.RAM6.INIT_08=256'h2073697a_6c617368_6e672066_0a57726f_00000000_6e67210a_63687475_652e2041;
-defparam bootram.RAM6.INIT_09=256'h00ffffff_65000000_792e6578_64756d6d_00000000_6e67210a_63687475_652e2041;
-defparam bootram.RAM6.INIT_0A=256'hc0a80a02_000031a0_00000000_00000000_00000000_ffffff00_ffff00ff_ff00ffff;
-defparam bootram.RAM6.INIT_0B=256'h00002fa0_000c0000_00190010_ffff0033_05050000_01010100_3fff0000_0050c285;
-defparam bootram.RAM6.INIT_0C=256'hffffffff_00000000_ffffffff_00003130_10101200_00002fb8_00002fb0_00002fa8;
-defparam bootram.RAM6.INIT_0D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_0E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_0F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_13=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_14=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_15=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_16=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_17=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_18=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_20=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_21=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_22=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_24=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_25=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_26=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_27=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_28=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_29=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_2A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_2B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_2C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_2D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_2E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_2F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_30=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_31=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_32=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_33=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_35=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_36=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_37=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_38=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM0.INIT_23=256'h800b80ee_a80c82a0_0b0b80ee_8380800b_822ebd38_80edcc08_802ea438_80edc808;
+defparam bootram.RAM0.INIT_24=256'h0b80eeac_80808280_eea80cf8_0b0b0b80_808080a4_b00c04f8_800b80ee_ac0c8290;
+defparam bootram.RAM0.INIT_25=256'h940b80ee_80c0a880_80eea80c_8c0b0b0b_80c0a880_eeb00c04_84800b80_0cf88080;
+defparam bootram.RAM0.INIT_26=256'h70085252_80edd408_5170a738_80eeb433_04ff3d0d_80eeb00c_80e0dc0b_ac0c0b0b;
+defparam bootram.RAM0.INIT_27=256'hb434833d_810b80ee_5270ee38_08700852_2d80edd4_edd40c70_38841280_70802e94;
+defparam bootram.RAM0.INIT_28=256'h38823d0d_09810685_800b802e_0b0b0b0b_802e8e38_80eea408_3d0d0b0b_0d040480;
+defparam bootram.RAM0.INIT_29=256'h3d225a79_80e13895_0d685b7a_0404ee3d_3f823d0d_0b0bf5d4_eea4510b_040b0b80;
+defparam bootram.RAM0.INIT_2A=256'h2e9e3879_79838086_3881ff39_80842e95_8b387983_83808524_80c93879_8380852e;
+defparam bootram.RAM0.INIT_2B=256'h890a0b81_880ca039_0c7a81e1_7a81e184_81e1800c_39890a0b_b13881ee_8380872e;
+defparam bootram.RAM0.INIT_2C=256'h5c7a7c2e_e5940c80_86397a81_81e4880c_0c8d397a_7a81e2c8_81e2c40c_e2c00c7a;
+defparam bootram.RAM0.INIT_2D=256'h99397983_2e9f3881_79838084_85248b38_38798380_80852ea7_225a7983_b838973d;
+defparam bootram.RAM0.INIT_2E=256'h53963d84_5c923d70_5c833983_5c873981_81883982_872e8c38_38798380_80862e8b;
+defparam bootram.RAM0.INIT_2F=256'h1d7f1d5b_415e5c7b_883d993d_5f40800b_84057d5b_3f800802_a73f8aa4_055241a9;
+defparam bootram.RAM0.INIT_30=256'h337b3481_055b5b79_1d963d7d_1f5e5c7b_38800b90_887c26ef_34811c5c_5b79337b;
+defparam bootram.RAM0.INIT_31=256'h26ef3880_1c5c867c_337b3481_1d5b5b79_5c7b1d60_0b881f5e_26ed3880_1c5c887c;
+defparam bootram.RAM0.INIT_32=256'h0d696b84_0d04ed3d_9d3f943d_26ef389a_1c5c867c_337b3481_1d5b5b79_5c7b1e61;
+defparam bootram.RAM0.INIT_33=256'he0e05195_538b5280_2e8c3875_94387580_56758b2e_9c387808_59837827_12085959;
+defparam bootram.RAM0.INIT_34=256'h19085eff_5ca05d88_3fa0578b_b0519597_a45280e1_8e387753_5777a326_aa3f80f5;
+defparam bootram.RAM0.INIT_35=256'h085f82e2_b33f8008_80d55d89_56750804_80e3d005_38758429_922682f8_98175675;
+defparam bootram.RAM0.INIT_36=256'h83ffff06_c93f8008_82cc39ab_822e9138_2e893875_7e567581_8c19085f_3980da5d;
+defparam bootram.RAM0.INIT_37=256'h193380f2_2e923894_577580f2_33568880_b5399519_ab973f82_92192251_4082bf39;
+defparam bootram.RAM0.INIT_38=256'h971a3357_0852800b_08538c19_33549019_76559619_06595156_962a8480_32703070;
+defparam bootram.RAM0.INIT_39=256'h06833881_882e0981_08595a77_800b8c1a_3f80085b_76519693_83388157_5775772e;
+defparam bootram.RAM0.INIT_3A=256'h19085377_19335490_2e923896_57577580_7d075151_07802570_70307072_5a779032;
+defparam bootram.RAM0.INIT_3B=256'h3352568b_05538c1a_54963dea_8d193370_5d81b339_7a4080d3_5193c43f_5280e1fc;
+defparam bootram.RAM0.INIT_3C=256'h8405b905_c85d7502_8d893f80_1a335256_8e1a538c_19337054_5d94398d_fc3f80c9;
+defparam bootram.RAM0.INIT_3D=256'h75080476_1a085856_e49c058c_75842980_2680c238_05567585_941933ff_3480ff39;
+defparam bootram.RAM0.INIT_3E=256'hb8057008_842980ee_239b3976_92192277_770ca239_39901908_762240a9_0840ae39;
+defparam bootram.RAM0.INIT_3F=256'h19085595_80cc5d8c_ad39775f_5680d25d_1a08710c_eeb80590_76842980_41568e39;
+defparam bootram.RAM1.INIT_00=256'hed38a439_58887826_77348118_57577533_973d7905_5a587719_800b833d_3ddc0554;
+defparam bootram.RAM1.INIT_01=256'h18588878_33773481_05575775_19973d79_3d5a5877_54800b83_953ddc05_a05da455;
+defparam bootram.RAM1.INIT_02=256'h73802e9d_5491d03f_80e2ac52_0d757053_0d04fd3d_c23f953d_8080519a_26ed3883;
+defparam bootram.RAM1.INIT_03=256'h39a05273_9aca3f95_518ef73f_86f63f81_72527251_3880c053_87e82e84_38a05373;
+defparam bootram.RAM1.INIT_04=256'he2cc5187_829e3f80_04fa3d0d_3f853d0d_73518ede_5186dd3f_80c05273_5186e53f;
+defparam bootram.RAM1.INIT_05=256'h3f84b23f_d40cab88_810b80ee_5190f83f_5280e388_91813f8b_80e2e851_d13f8852;
+defparam bootram.RAM1.INIT_06=256'hdc3f858c_8fca3f86_3f800851_e83f8598_8fb03f86_3f800851_803f84c4_859b3f83;
+defparam bootram.RAM1.INIT_07=256'h518daa3f_85528008_87538380_fb3f8380_93d73f84_52800851_84a63f73_3f800854;
+defparam bootram.RAM1.INIT_08=256'h86519485_b2528380_948f3f8a_83808451_3f8ab252_80519499_da528380_93dd3f8c;
+defparam bootram.RAM1.INIT_09=256'h5193e63f_52838082_3f80c7db_875193f1_b2528380_93fb3f8a_83808551_3f8ab252;
+defparam bootram.RAM1.INIT_0A=256'h3f800856_05518d9a_3f883dfc_b43fadd9_90ce51ab_518da33f_a4973f80_83809251;
+defparam bootram.RAM1.INIT_0B=256'he3ac5280_38845380_098106ad_82fdee2e_22555573_80088e05_80c93876_8008802e;
+defparam bootram.RAM1.INIT_0C=256'h9c3f7351_8e8a3f85_16705254_8f993f94_80e3b451_80089a38_80cb953f_08900551;
+defparam bootram.RAM1.INIT_0D=256'he53f90e1_fe3d0d84_3fff9e39_ea3f8b84_8c9f3fa3_51999e3f_39745275_84973f88;
+defparam bootram.RAM1.INIT_0E=256'hfb3f8452_82ac5189_5184913f_3f9f5280_805184b5_8c3f9f52_8abc3f87_3f86903f;
+defparam bootram.RAM1.INIT_0F=256'h83ea3f82_90529051_5189e13f_f73f82ac_52885183_89ee3f88_3f82ac51_84518484;
+defparam bootram.RAM1.INIT_10=256'he45189b8_83ce3f80_9f529c51_5189c53f_db3f80e4_52805183_3f82539f_ac5189d4;
+defparam bootram.RAM1.INIT_11=256'h0c810b80_0b81e084_83b23f89_9f528151_5183d63f_389f529e_728025df_3fff1353;
+defparam bootram.RAM1.INIT_12=256'h087081cf_88fe3f76_5780e451_07720c57_087080e0_81e08070_04fa3d0d_0c843d0d;
+defparam bootram.RAM1.INIT_13=256'h5281518f_88805381_80559054_780c5688_7080e007_ef3f7608_80e45188_06780c56;
+defparam bootram.RAM1.INIT_14=256'h085280e4_8fa53f80_82528151_54888053_88805590_518da03f_5280e4b4_be3f8008;
+defparam bootram.RAM1.INIT_15=256'h53727627_70565480_7a575781_fa3d0d78_883d0d04_810b800c_3fa5d83f_d0518d87;
+defparam bootram.RAM1.INIT_16=256'h53df3974_80558113_ff2e8338_33527181_38805471_70802e83_70335252_9e387217;
+defparam bootram.RAM1.INIT_17=256'h80e4f052_dc348653_810b80ee_04fe3d0d_0c883d0d_81517080_802e8338_74075170;
+defparam bootram.RAM1.INIT_18=256'h34865487_0b80eedc_74bd3881_eedc3355_f93d0d80_843d0d04_80c5ed3f_80eddc51;
+defparam bootram.RAM1.INIT_19=256'hf33f8008_527551fe_2e9d3886_06557480_800881ff_51b4f23f_825280d0_3d705456;
+defparam bootram.RAM1.INIT_1A=256'h04810b80_0c893d0d_eddc0b80_c5a23f80_eddc5180_53755280_748d3886_81ff0655;
+defparam bootram.RAM1.INIT_1B=256'h34845487_0b80eed8_74b93881_eed83355_fb3d0d80_edd80c04_e4ec0880_eed83480;
+defparam bootram.RAM1.INIT_1C=256'h0551fe90_52873dfc_2e993884_06557480_800881ff_51b4923f_8c5280d0_3dfc0553;
+defparam bootram.RAM1.INIT_1D=256'h77568454_04fb3d0d_0c873d0d_edd80b80_edd80c80_86387580_ff065574_3f800881;
+defparam bootram.RAM1.INIT_1E=256'h0b80eed8_edd80c81_38750880_74802e8d_81ff0655_d83f8008_80d051b2_75538c52;
+defparam bootram.RAM1.INIT_1F=256'h81e08c0c_80eee00c_08060770_7180eee0_09737506_803d0d73_873d0d04_3474800c;
+defparam bootram.RAM1.INIT_20=256'h0c51823d_0c81e098_7080eee4_e4080607_067180ee_73097375_04803d0d_51823d0d;
+defparam bootram.RAM1.INIT_21=256'h8a528051_04ff3d0d_0c843d0d_c73f7280_53805181_0d747053_3f04fe3d_0d0481af;
+defparam bootram.RAM1.INIT_22=256'h157481ff_2e903881_54547280_7081ff06_56567433_3d0d7779_3d0d04fb_81b63f83;
+defparam bootram.RAM1.INIT_23=256'h3d0d04fe_51cd3f83_0d735280_0d04ff3d_800c873d_e539800b_5581913f_06537652;
+defparam bootram.RAM1.INIT_24=256'h0d735280_0d04ff3d_800c843d_e73f800b_52725180_ffbd3f8a_53705253_3d0d7476;
+defparam bootram.RAM1.INIT_25=256'h73a02982_04ff3d0d_34823d0d_80ede412_028f0533_3d0d7251_3d0d0480_51dd3f83;
+defparam bootram.RAM1.INIT_26=256'h33527251_80ede413_3d0d8053_3d0d04fe_0c535183_05702272_1080e4f8_90800575;
+defparam bootram.RAM1.INIT_27=256'h78565474_fc3d0d76_843d0d04_7325e538_81135382_7251ce3f_e8133352_c63f80ed;
+defparam bootram.RAM1.INIT_28=256'ha0298290_51de3f73_388d5273_09810687_5372812e_ede41433_06953880_8a2e0981;
+defparam bootram.RAM1.INIT_29=256'h80058811_a0298290_fe3d0d74_863d0d04_748c150c_802ef838_14085372_80055484;
+defparam bootram.RAM1.INIT_2A=256'h880c80ed_800b81a8_04ff3d0d_0c843d0d_08537280_85389012_5370802e_085252ff;
+defparam bootram.RAM1.INIT_2B=256'h04fd3d0d_0c833d0d_0b81a888_0c518180_2a81a884_800c7088_ff0681a8_f0227081;
+defparam bootram.RAM1.INIT_2C=256'h06515151_862a7081_a8900870_81863881_5171802e_55535481_05970533_76780288;
+defparam bootram.RAM1.INIT_2D=256'h51515170_2a708106_90087081_900c81a8_900b81a8_a88c0c81_10810781_70f13872;
+defparam bootram.RAM1.INIT_2E=256'h3880e851_71802eb1_802eba38_51515170_70813251_2a708106_90087087_f13881a8;
+defparam bootram.RAM1.INIT_2F=256'h81a88c08_5170f138_81065151_70812a70_81a89008_81a8900c_38a05170_71812e83;
+defparam bootram.RAM1.INIT_30=256'h3d0d04fd_70800c85_81a8900c_3980c00b_39815188_ff1252cc_81055634_51707470;
+defparam bootram.RAM1.INIT_31=256'h38721081_515170f1_70810651_0870862a_5481a890_05335553_02880597_3d0d7678;
+defparam bootram.RAM1.INIT_32=256'h06515151_812a7081_a8900870_a8900c81_90517081_2e843881_d0517180_a88c0c81;
+defparam bootram.RAM1.INIT_33=256'h2e80c538_cf387180_70802e80_51515151_06708132_872a7081_a8900870_70f13881;
+defparam bootram.RAM1.INIT_34=256'h70810651_0870812a_0c81a890_7081a890_83389051_5171812e_8c0c80d0_733381a8;
+defparam bootram.RAM1.INIT_35=256'h14ff1353_2e8e3881_51517080_81325151_70810670_0870872a_3881a890_515170f1;
+defparam bootram.RAM1.INIT_36=256'h54805372_fd3d0d75_853d0d04_5170800c_a8900c80_80c00b81_81518a39_54ffb739;
+defparam bootram.RAM1.INIT_37=256'he239853d_38811353_c77127f1_515180e5_08707331_5281b8ac_81b8ac08_74259b38;
+defparam bootram.RAM1.INIT_38=256'h8c0c80f9_ff0b8280_8280840c_800cef0b_e00b8280_80880c81_0dff0b82_0d04ff3d;
+defparam bootram.RAM1.INIT_39=256'h80880870_fb3d0d82_833d0d04_8025f138_ff115170_8405540c_9fa87270_a4528751;
+defparam bootram.RAM1.INIT_3A=256'h72517308_802e8f38_76065271_a4555574_810b80f9_51528053_08710658_0982808c;
+defparam bootram.RAM1.INIT_3B=256'hff3d0d73_873d0d04_7325dc38_57555387_84157610_8f398113_82808c0c_52712d74;
+defparam bootram.RAM1.INIT_3C=256'h06828088_88087072_70098280_5181722b_0575710c_2980f9a4_9f387184_52718726;
+defparam bootram.RAM1.INIT_3D=256'h0c557090_0881e0c4_05227670_0284059a_02960522_04fe3d0d_833d0d04_0c535152;
+defparam bootram.RAM1.INIT_3E=256'h06515170_a0087084_cc0c81b8_810b81e0_04803d0d_51843d0d_e0c80c53_2b720781;
+defparam bootram.RAM1.INIT_3F=256'h08708106_0d81b8a0_0c04fe3d_7181e0c0_0d04de3f_cc0c823d_820b81e0_802ef338;
+defparam bootram.RAM2.INIT_00=256'h70810651_3971812a_8080529a_0c535381_71902a71_b8a00875_2e933881_54527280;
+defparam bootram.RAM2.INIT_01=256'h81b8a008_04803d0d_0c843d0d_72527180_3fff9e3f_8451f8c6_8b3880e5_5271802e;
+defparam bootram.RAM2.INIT_02=256'h70902b88_028e0522_04ff3d0d_0c823d0d_80800b80_2ef23881_51517080_7080c006;
+defparam bootram.RAM2.INIT_03=256'h0d04fd3d_cc0c833d_840b81e0_802ef338_06515170_a0087090_0c5281b8_0781e0cc;
+defparam bootram.RAM2.INIT_04=256'h7327e638_81135385_52acc53f_14703352_f7983f72_8638ba51_5372802e_0d755480;
+defparam bootram.RAM2.INIT_05=256'h80ed3f87_80e58851_70335356_81113354_82113355_83113356_fb3d0d77_853d0d04;
+defparam bootram.RAM2.INIT_06=256'h7680258f_5d5b5957_2a515b5f_7030709f_05bb0533_61630290_3d0d7c7e_3d0d04f6;
+defparam bootram.RAM2.INIT_07=256'h7651b4ba_80537752_79557854_77269438_76305777_ad51782d_8a387952_3875802e;
+defparam bootram.RAM2.INIT_08=256'h803d0d02_8c3d0d04_3351782d_80e59405_d23f8008_527651b4_ffbd3f77_3f800851;
+defparam bootram.RAM2.INIT_09=256'h337081ff_5c5a5878_5208a29c_70708405_3d0d8c3d_3d0d04f7_f6803f82_8b053351;
+defparam bootram.RAM2.INIT_0A=256'h597580f0_19703357_80db3881_2e098106_065675a5_387681ff_802e81d1_06575775;
+defparam bootram.RAM2.INIT_0B=256'h81953975_2e819e38_8a387580_7580e324_e32eb938_a0387580_7580f024_2e80fb38;
+defparam bootram.RAM2.INIT_0C=256'h80f53975_2e80db38_387580f3_80f5248b_2eac3875_397580f5_c638818b_80e42e80;
+defparam bootram.RAM2.INIT_0D=256'h19710852_da397784_51792d80_56805275_12335259_77841983_3880ec39_80f82eba;
+defparam bootram.RAM2.INIT_0E=256'h92397784_81538a52_55a29c54_52595680_84197108_53903977_a29c5480_59568055;
+defparam bootram.RAM2.INIT_0F=256'h59567633_19710859_9e397784_51fdd03f_53905275_a29c5480_59568055_19710852;
+defparam bootram.RAM2.INIT_10=256'h0c8b3d0d_39800b80_1959fea3_2dec3981_58335179_76708105_8e388052_5675802e;
+defparam bootram.RAM2.INIT_11=256'h3d0d04fd_70f13882_06515151_882a7081_a0900870_803d0d81_a0940c04_04810b81;
+defparam bootram.RAM2.INIT_12=256'hff0681a0_3f7683ff_555354d0_80c08007_80060770_ff067b8c_05337980_3d0d0297;
+defparam bootram.RAM2.INIT_13=256'hffaa3f81_802e8938_0c735173_0781a090_7180c280_81a0900c_a0800c72_980c7781;
+defparam bootram.RAM2.INIT_14=256'h10157022_278f3872_80537274_7a545555_3d0d7678_3d0d04fc_70800c85_a0800851;
+defparam bootram.RAM2.INIT_15=256'hec397180_902a0552_ffff0672_8d387183_5170802e_3971902a_555351ee_73058115;
+defparam bootram.RAM2.INIT_16=256'h3d0d04ff_f40c5485_700880ee_b6a23f76_80eeec51_86537552_04fd3d0d_0c863d0d;
+defparam bootram.RAM2.INIT_17=256'h0d029605_0d04fd3d_f338833d_52708025_12ff1252_80720c88_fc528951_3d0d80ee;
+defparam bootram.RAM2.INIT_18=256'h80517080_7225ee38_12525289_38811288_72742e8e_52702254_80eef852_2253800b;
+defparam bootram.RAM2.INIT_19=256'h0884050c_89387680_8008802e_5856c73f_ffff0653_787a7183_04fa3d0d_0c853d0d;
+defparam bootram.RAM2.INIT_1A=256'h14545589_38811588_71802e8f_88155552_55557308_80eef855_80eefc0b_ad398008;
+defparam bootram.RAM2.INIT_1B=256'h3dd60552_933d5392_0d867054_0d04f13d_140c883d_73237684_a3ac3f75_7525eb38;
+defparam bootram.RAM2.INIT_1C=256'h8a800b8b_a2052381_80028405_b4e23f90_3ddc0551_88055291_7353923d_54b4f13f;
+defparam bootram.RAM2.INIT_1D=256'h3d238002_c0910b8d_aa052380_80028405_3d238180_23800b8c_8405a605_3d238002;
+defparam bootram.RAM2.INIT_1E=256'h23983d22_8405ae05_3f800802_0551fdb7_52913de4_5e80538a_23685d66_8405ae05;
+defparam bootram.RAM2.INIT_1F=256'hd4055269_ac53913d_05be0523_23800284_800b913d_05ba0523_3d220284_903d2396;
+defparam bootram.RAM2.INIT_20=256'h3d529a3d_2386539b_800b973d_3d0d805b_3d0d04e8_a58b3f91_e6840551_80c02981;
+defparam bootram.RAM2.INIT_21=256'h80e20523_22028405_0280f205_51b3c13f_9a3df805_80eeec52_cf3f8653_f20551b3;
+defparam bootram.RAM2.INIT_22=256'h4659845c_45a33d08_44a13d08_f005436e_3dc41143_5a800b9b_08800858_f7f73f80;
+defparam bootram.RAM2.INIT_23=256'h90807131_1a787c31_58750870_8c3d5684_05fc0640_a33d0883_a13d085f_905d6e5e;
+defparam bootram.RAM2.INIT_24=256'h16088306_738c3894_73830654_802e9a38_75085473_3873760c_73752784_51565a55;
+defparam bootram.RAM2.INIT_25=256'h05570817_3f757084_7651a3dd_94160852_3f750853_b051efee_883880e5_5473802e;
+defparam bootram.RAM2.INIT_26=256'h04ea3d0d_3f9a3d0d_2a51f6fd_c0597882_26843880_ac3878bf_778025ff_ff195957;
+defparam bootram.RAM2.INIT_27=256'h23818080_800b953d_80ca0523_79028405_1f94055a_943d237f_818a800b_6b6e4040;
+defparam bootram.RAM2.INIT_28=256'h08466847_2380eef4_0580d205_23800284_5a79963d_80c08007_ce052369_02840580;
+defparam bootram.RAM2.INIT_29=256'h983d7053_913d7053_80d20523_79028405_8008095a_5cfae03f_933d7052_80538a52;
+defparam bootram.RAM2.INIT_2A=256'h3fa93902_cb3feddd_3f7a51f6_dc51f7d7_923880e5_ff065a79_3f800881_5c5e8ac8;
+defparam bootram.RAM2.INIT_2B=256'h811c5c86_79337b34_7c1f5b5b_805c7b1d_54908053_5d94557b_60586b57_7f5a6d59;
+defparam bootram.RAM2.INIT_2C=256'h05a20523_3d220284_8a3d238d_02ae0522_3d0d7f58_3d0d04f7_fd893f98_7c26ef38;
+defparam bootram.RAM2.INIT_2D=256'h51fe9e3f_5391527d_8b3df805_7e558854_05237756_028405a6_8b3d2380_88185776;
+defparam bootram.RAM2.INIT_2E=256'h05b50534_34840284_860b8f3d_05b20523_90800284_0b8e3d23_ee3d0d81_8b3d0d04;
+defparam bootram.RAM2.INIT_2F=256'h80085294_f33f8453_affe3fea_3dec0551_80085294_a33f8653_b60523ea_81028405;
+defparam bootram.RAM2.INIT_30=256'h80598058_0843025c_d73f8008_b0fb3fea_3df60551_53805294_afee3f86_3df20551;
+defparam bootram.RAM2.INIT_31=256'h5b867b26_7a34811b_e5a81b33_7a1c5a80_8653805b_e4055490_9c55943d_80578056;
+defparam bootram.RAM2.INIT_32=256'h9d38901d_09810682_7d90862e_11225f5d_aa3d088e_04d93d0d_3f943d0d_ef38fbcb;
+defparam bootram.RAM2.INIT_33=256'h5a79812e_ee397a22_f5b53f86_80e68c51_8d387952_5b799b26_29f2055b_ac3d0884;
+defparam bootram.RAM2.INIT_34=256'h09810686_798c842e_841b225a_0686d438_802e0981_225a7990_e238821b_09810686;
+defparam bootram.RAM2.INIT_35=256'h87fd3f80_1d70525f_88853fa8_1d705240_86b9389e_2e098106_225a7981_c638861b;
+defparam bootram.RAM2.INIT_36=256'h865380ee_38a73d5a_8008868f_3f80085c_0551adb0_a93dffa8_80eef452_08438453;
+defparam bootram.RAM2.INIT_37=256'h851b3302_33a23d34_0523841b_840580fe_821b2202_22a13d23_ae8e3f7a_ec527951;
+defparam bootram.RAM2.INIT_38=256'h547f53aa_db3f8470_e40551ad_7952a93d_05238653_84058182_05348202_84058181;
+defparam bootram.RAM2.INIT_39=256'h3df40551_537f52a9_adbe3f79_1d527a51_5b865398_02818e05_5aadcd3f_3dea0552;
+defparam bootram.RAM2.INIT_3A=256'h3ddc0554_5d9c55a9_7c587c57_7c5a7c59_ada63f02_7a527e51_3d5f8653_adb23f9e;
+defparam bootram.RAM2.INIT_3B=256'h802e0981_ee397d90_f9993f84_7c26ef38_811c5c86_79337b34_7f1d5b5b_7d537b1d;
+defparam bootram.RAM2.INIT_3C=256'h06515a79_882a708f_84d13879_2e098106_5b5b6084_708c2a43_901d7022_0684e438;
+defparam bootram.RAM2.INIT_3D=256'h821d51ab_80e5a852_7e5e8653_7e84b438_ffff065f_861b2280_0684c038_852e0981;
+defparam bootram.RAM2.INIT_3E=256'h815c7d87_80088338_5caba93f_5470535b_5580eef4_7e901c62_8338815e_bf3f8008;
+defparam bootram.RAM2.INIT_3F=256'h812e81bb_405d407f_1c22ec11_891b3382_5184b83f_1d529c1d_84813888_387b802e;
+defparam bootram.RAM3.INIT_00=256'h3879537d_7d7a2e8f_5d5d4240_1f841122_087a08a4_de388c1b_09810683_387f912e;
+defparam bootram.RAM3.INIT_01=256'h08802e83_80084280_5df5c33f_1d22535d_1de41d82_83bd39ac_51f2843f_5280e6ac;
+defparam bootram.RAM3.INIT_02=256'h5379527f_9c3d4088_51ab9d3f_537d5279_3d5f5a88_499a3d99_993d237f_a6387a22;
+defparam bootram.RAM3.INIT_03=256'h527d51aa_3f885379_7951aafc_ffb40552_8853a93d_3d236047_821b2297_51ab913f;
+defparam bootram.RAM3.INIT_04=256'h38805b7f_887c26ef_34811c5c_5b79337b_1d7c1f5b_3d5e5c7b_7c557e84_f33f7b56;
+defparam bootram.RAM3.INIT_05=256'h1b08a41e_82ad398c_085a792d_38618405_887b26ef_34811b5b_0284051c_1b5a7933;
+defparam bootram.RAM3.INIT_06=256'h0681a238_832e0981_1a335a79_82953981_2e81bb38_8a387d88_427d832e_7033405b;
+defparam bootram.RAM3.INIT_07=256'h41800880_813f8008_7c2251f4_0681f438_912e0981_5c5e5c79_1e891233_ac1d80c0;
+defparam bootram.RAM3.INIT_08=256'hd73f963d_527d51a9_5e88537a_3d9b3d5c_23794b98_7c229b3d_8c1c085a_2e80fe38;
+defparam bootram.RAM3.INIT_09=256'h527a51a9_a93dcc05_794d8853_229d3d23_085a821d_cb3f901c_527f51a9_4088537d;
+defparam bootram.RAM3.INIT_0A=256'h7b34811c_5b5b7933_7b1d7c1f_843d5e5c_567e557e_a9aa3f7e_7a527d51_b33f8853;
+defparam bootram.RAM3.INIT_0B=256'h05085a79_ef386084_5b887b26_1c34811b_33028405_7f1b5a79_ef38805b_5c887c26;
+defparam bootram.RAM3.INIT_0C=256'h7e028405_80cd0534_7e028405_7e953d34_e41d5d5d_de39ac1d_e5a03f80_2d80e951;
+defparam bootram.RAM3.INIT_0D=256'h5bf1cc3f_943d7052_7e536052_80d20523_22028405_3d23861a_841a2296_80ce0523;
+defparam bootram.RAM3.INIT_0E=256'h7d547a53_7b567c55_80ce0523_79028405_8008095a_51f1c03f_812a527c_8008537b;
+defparam bootram.RAM3.INIT_0F=256'h700880ef_27a43876_55537274_80efc808_3d0d800b_3d0d04fc_f5f73fa9_7f526151;
+defparam bootram.RAM3.INIT_10=256'he738ff51_53737326_8b398113_85387251_2e098106_53517075_71088c13_d0545651;
+defparam bootram.RAM3.INIT_11=256'h08547387_3880efc8_088025ba_ffb93f80_71535755_3d0d7779_3d0d04fb_70800c86;
+defparam bootram.RAM3.INIT_12=256'h822b7608_73101470_efcc0c54_11870680_efcc0881_0c8e3980_1480efc8_26893881;
+defparam bootram.RAM3.INIT_13=256'h52738429_54865375_10800805_94398008_efd41451_53755280_0c515486_80efd012;
+defparam bootram.RAM3.INIT_14=256'h80081080_08249938_80547380_51fed83f_fd3d0d75_873d0d04_51a6ed3f_80efd405;
+defparam bootram.RAM3.INIT_15=256'h3d0d7570_3d0d04fd_73800c85_c33f8154_527651a6_80efd405_53738429_08055486;
+defparam bootram.RAM3.INIT_16=256'h54565452_800c5253_16337107_2b720783_14337088_902b0782_71982b71_33811233;
+defparam bootram.RAM3.INIT_17=256'h72315256_8b3d2270_83ffff06_76a83873_22565957_7f80f0b0_f93d0d7d_853d0d04;
+defparam bootram.RAM3.INIT_18=256'hffff068d_c0397383_76742380_b4055154_902980f0_90291470_80d33873_54738326;
+defparam bootram.RAM3.INIT_19=256'hb40551a5_902980f0_8a3d5273_15548853_38749029_748326ad_31575754_3d227072;
+defparam bootram.RAM3.INIT_1A=256'h04fc3d0d_39893d0d_811656ec_51e3a53f_33535474_38751770_75782791_b33f8056;
+defparam bootram.RAM3.INIT_1B=256'h140cb5e4_800b828c_8288140c_7323800b_b4545480_800b80f0_80f0b023_029a0522;
+defparam bootram.RAM3.INIT_1C=256'h3d0d800b_3d0d04f4_27d93886_54548374_14829014_ef9b3f81_22740551_5280f0b0;
+defparam bootram.RAM3.INIT_1D=256'hff2680d6_5b5d7981_82881a08_81be3875_06515675_81327081_5c847c2c_80f0b45a;
+defparam bootram.RAM3.INIT_1E=256'h728d3270_8a327030_81ff0670_c5388008_08ff2e80_e2ea3f80_055b7b51_38781a88;
+defparam bootram.RAM3.INIT_1F=256'h82881908_81055d34_5d777b70_2e833881_58587680_53515951_71802507_30728025;
+defparam bootram.RAM3.INIT_20=256'h80d2387c_1908802e_b1388288_ff7a27ff_811a5a81_828c1a0c_1a0c800b_81058288;
+defparam bootram.RAM3.INIT_21=256'h19085588_ab388288_5675802e_bf387822_568b7627_828c1b0c_19088111_9138828c;
+defparam bootram.RAM3.INIT_22=256'hb0227c05_ef3880f0_58887826_77348118_57577533_771a781a_833d5b58_1954800b;
+defparam bootram.RAM3.INIT_23=256'h388e3d0d_7c27fea9_1a5a5c83_811c8290_828c1a0c_1a0c800b_800b8288_51f2a83f;
+defparam bootram.RAM3.INIT_24=256'ha23f873d_528151eb_ff065384_9054759f_c4238055_567580f9_029e0522_04fb3d0d;
+defparam bootram.RAM3.INIT_25=256'h81bd3881_5372802e_81065151_70812a70_81b08008_04fa3d0d_c422800c_0d0480f9;
+defparam bootram.RAM3.INIT_26=256'h882980ed_80edf808_2681a438_728c9abe_a39f1453_800ce7a0_810b81b0_b0840854;
+defparam bootram.RAM3.INIT_27=256'h73258738_5380ce90_31525851_e5ea8071_edf80c98_832c7080_11840570_f8083174;
+defparam bootram.RAM3.INIT_28=256'h2980f988_70902c75_2270902b_5380f8f4_38ffb1f0_b1f02585_8c3972ff_80ce9053;
+defparam bootram.RAM3.INIT_29=256'h84087f31_902b80f9_f8f82270_2c732980_902b7090_f8f62270_f9880c80_08167080;
+defparam bootram.RAM3.INIT_2A=256'h73258638_56548fff_555b5651_57555351_70872c52_0c731805_7f80f984_71902c29;
+defparam bootram.RAM3.INIT_2B=256'h3d0d04fd_fe873f88_ff065253_137083ff_81539080_258438f0_3972f081_8fff538a;
+defparam bootram.RAM3.INIT_2C=256'h55239073_73708205_545480c0_80f8f470_51e3ed3f_b9a95281_51fdfa3f_3d0d9080;
+defparam bootram.RAM3.INIT_2D=256'h0d04ea3d_800c853d_810b81b0_0b94150c_90150c80_e5ea800b_84152398_2382800b;
+defparam bootram.RAM3.INIT_2E=256'h7381ff2e_70335154_57557417_84059d05_c63f8002_52685199_545780c0_0d883d70;
+defparam bootram.RAM3.INIT_2F=256'h8b398115_85388154_2e098106_54738199_16703351_06943874_aa2e0981_9d387381;
+defparam bootram.RAM3.INIT_30=256'hf63f8055_52795198_70545484_3d0d863d_3d0d04f9_73800c98_d1388054_55be7527;
+defparam bootram.RAM3.INIT_31=256'h04810b81_0c893d0d_81557480_81068338_08752e09_9ed63f80_d0527351_845380e6;
+defparam bootram.RAM3.INIT_32=256'h80518e95_55e5d03f_80e6d452_ff067053_3f800881_b43f8f9f_fc3d0d92_e0940c04;
+defparam bootram.RAM3.INIT_33=256'he7a451dc_74b73880_51818739_3880e6ec_51547388_70810651_08708d2a_3f81b8b4;
+defparam bootram.RAM3.INIT_34=256'hac51e0b8_8ddb3f82_853f8151_e7d051dc_2e9c3880_3f800880_0a51feb6_993f9880;
+defparam bootram.RAM3.INIT_35=256'hbd3880e8_8008802e_51fed83f_3f8c800a_8851dbea_f93f80e8_800a5183_3f745298;
+defparam bootram.RAM3.INIT_36=256'hac51dff8_dbc03f82_80e8dc51_5197c03f_528c800a_5380ffff_3f838080_b051dbd6;
+defparam bootram.RAM3.INIT_37=256'hbc51db9a_883980e9_5183ab3f_3f805280_ac51dfe8_dbb03f82_80e98051_3ffeda3f;
+defparam bootram.RAM3.INIT_38=256'h5280ea88_80c05373_e82e8438_a0537387_3d0d7554_8c0c04fd_047180f9_3f863d0d;
+defparam bootram.RAM3.INIT_39=256'h04fe3d0d_2d853d0d_38735172_72802e85_f98c0853_d9be3f80_72527251_51e4883f;
+defparam bootram.RAM3.INIT_3A=256'h2d843d0d_38805172_72802e85_f98c0853_d99a3f80_c0528051_d9a23f80_a0528051;
+defparam bootram.RAM3.INIT_3B=256'h38820b80_802e80ec_54815571_81065153_08862a70_3fff0b80_9a518dca_04fc3d0d;
+defparam bootram.RAM3.INIT_3C=256'h8a3987e8_802e8e38_388a5471_8280248a_2e9b3871_54718280_535580e4_08868006;
+defparam bootram.RAM3.INIT_3D=256'h088a2c70_2a8c0680_fd3f7188_5285518c_853f8008_5484518d_2e8338ff_54718480;
+defparam bootram.RAM3.INIT_3E=256'h8c0680ed_3f71822b_5452d99a_c0555351_980c80ea_337080f9_80eb8011_83067207;
+defparam bootram.RAM3.INIT_3F=256'h2e098106_a6387481_0c74822e_7480f990_082e9838_7480f990_52d9b33f_fc110852;
+defparam bootram.RAM4.INIT_00=256'hfe9f3f73_80f9940c_2e8e3873_80f99408_06963873_822e0981_3f9e3974_a338feb9;
+defparam bootram.RAM4.INIT_01=256'hf9900cff_3f800b80_08518bdf_d5da3f80_04fd3d0d_3f863d0d_99518c8a_51fde83f;
+defparam bootram.RAM4.INIT_02=256'h528451de_8a3fbee1_529c518c_3f81ae80_98518c93_e93f8d52_0c99518b_0b80f994;
+defparam bootram.RAM4.INIT_03=256'h7380082e_518bb73f_8bed3f84_53548451_f49f0670_08908007_8bcc3f80_9b3f8451;
+defparam bootram.RAM4.INIT_04=256'hc63f853d_5280518b_08848007_8ba03f80_9e3f8051_ead851e1_53735280_8d388008;
+defparam bootram.RAM4.INIT_05=256'hc0807271_ffff5282_07595683_0681d00a_077ed00a_0681d00a_0d7cd00a_0d04f63d;
+defparam bootram.RAM4.INIT_06=256'hd4e6770c_3f8a5982_8a51dc80_ab99770c_dc8a3f81_770c8a51_dc923f71_0c578a51;
+defparam bootram.RAM4.INIT_07=256'h70852a82_7081ff06_83ffff06_dbe63f75_770c7851_5a819986_3f80e180_7851dbf4;
+defparam bootram.RAM4.INIT_08=256'h71730707_832ba006_10900674_73070773_2a880671_84067281_0771832a_0671872a;
+defparam bootram.RAM4.INIT_09=256'h2a820671_882a7085_7307077a_81800673_2b630670_c0067787_76852b80_7081ff06;
+defparam bootram.RAM4.INIT_0A=256'h07077081_a0067173_0674832b_07731090_06717307_72812a88_832a8406_872a0771;
+defparam bootram.RAM4.INIT_0B=256'hffff066d_7b077083_0770882b_06737307_06708180_77872b6d_2b80c006_ff067685;
+defparam bootram.RAM4.INIT_0C=256'h81998177_53dabd3f_52575d56_52535157_555b5158_5157525a_6b445253_0c515158;
+defparam bootram.RAM4.INIT_0D=256'h2a820671_ff067085_73077081_81ff0670_76902a70_2a968006_b33f7590_0c7851da;
+defparam bootram.RAM4.INIT_0E=256'h07077081_a0067173_0674832b_07731090_06717307_72812a88_832a8406_872a0771;
+defparam bootram.RAM4.INIT_0F=256'h2b80c006_90067185_882a7010_81ff067a_872b0770_70720778_2b80c006_ff067685;
+defparam bootram.RAM4.INIT_10=256'h525a5a57_55535158_405b5151_0c515667_06740768_2b83fe80_2b077088_71077287;
+defparam bootram.RAM4.INIT_11=256'hff067085_ff067081_3f7783ff_7851d9a4_9985770c_a1805681_d9b23f81_51515752;
+defparam bootram.RAM4.INIT_12=256'ha0067173_0674832b_07731090_06717307_72812a88_832a8406_872a0771_2a820671;
+defparam bootram.RAM4.INIT_13=256'h70852a82_077a882a_06737307_06708180_77872b7f_2b80c006_ff067685_07077081;
+defparam bootram.RAM4.INIT_14=256'h71730707_832ba006_10900674_73070773_2a880671_84067281_0771832a_0671872a;
+defparam bootram.RAM4.INIT_15=256'h7083ffff_882b7b07_73070770_81800673_2b690670_c0067787_76852b80_7081ff06;
+defparam bootram.RAM4.INIT_16=256'hfb3f81c1_5c5653d7_51575257_51585253_525a555b_52535157_51586b44_066d0c51;
+defparam bootram.RAM4.INIT_17=256'h7081ff06_06707307_2a7081ff_80067890_77902a96_51d7ed3f_83770c78_80558199;
+defparam bootram.RAM4.INIT_18=256'h832ba006_10900674_73070773_2a880671_84067281_0771832a_0671872a_70852a82;
+defparam bootram.RAM4.INIT_19=256'h882a7010_7307077a_81800673_2b610670_c0067787_76852b80_7081ff06_71730707;
+defparam bootram.RAM4.INIT_1A=256'h0c515269_ffff066a_75077083_0770882b_06717307_72872b66_2b80c006_90067185;
+defparam bootram.RAM4.INIT_1B=256'h52d6d93f_780c7952_3f998570_5952d6e4_5b575151_5158525a_51585253_425a545b;
+defparam bootram.RAM4.INIT_1C=256'h780c7952_3f888070_7851d6c0_80f0770c_51d6c93f_71770c78_51d6d13f_80770c78;
+defparam bootram.RAM4.INIT_1D=256'h8c3d0d04_51d69d3f_71770c78_51d6a53f_71770c78_51d6ad3f_71770c78_52d6b53f;
+defparam bootram.RAM4.INIT_1E=256'hb23d0d80_3d0d04ff_22800c87_cc3f863d_80d05183_05538052_54873dfc_fb3d0d82;
+defparam bootram.RAM4.INIT_1F=256'hdaad3f81_80eb9051_53829452_26903877_57778293_12085859_d73d0884_d53d0880;
+defparam bootram.RAM4.INIT_20=256'h3f800808_c15cced0_75080480_ebdc0556_75842980_2681d438_16567596_de39ff9f;
+defparam bootram.RAM4.INIT_21=256'h0b81e2c4_e2c00c80_890a0b81_81e1880c_840c800b_800b81e1_81e1800c_5e890a0b;
+defparam bootram.RAM4.INIT_22=256'h8caa3f80_3f80085e_8c398ca6_e5940c81_0c800b81_0b81e488_e2c80c80_0c800b81;
+defparam bootram.RAM4.INIT_23=256'h8c170852_90170853_5c80ea39_065e80d6_0883ffff_fed63f80_5c80fa39_085f80c6;
+defparam bootram.RAM4.INIT_24=256'h2e863880_06567580_800881ff_518a983f_3980f9c8_c55c80d5_89d33f80_80f9c851;
+defparam bootram.RAM4.INIT_25=256'h80d03dfe_d75ca639_88ba3f80_8c170851_90170852_39941753_80c25cb9_c45cbe39;
+defparam bootram.RAM4.INIT_26=256'h3f8339a0_8051f7c6_d35c8052_5c8f3980_c63f80d2_1708518b_1708528c_80055390;
+defparam bootram.RAM4.INIT_27=256'h77348118_57577533_d23d7905_58771980_0b833d5a_ec055480_80d03dfd_5c829455;
+defparam bootram.RAM4.INIT_28=256'hff5182f3_51ced73f_0d80ecb8_0d04803d_3f80d03d_8251e0ff_ec388380_58887826;
+defparam bootram.RAM4.INIT_29=256'h8a3d3476_17575473_b7387581_54807425_74ff1656_5a575758_7a7c7f7f_3ff83d0d;
+defparam bootram.RAM4.INIT_2A=256'h81ff0654_c63f8008_ff0651d1_05527781_538a3dfc_a1053482_33028405_70810558;
+defparam bootram.RAM4.INIT_2B=256'h5580de56_02a30533_04fa3d0d_0c8a3d0d_81547380_8538c139_3f73802e_8a51d2f4;
+defparam bootram.RAM4.INIT_2C=256'h04f93d0d_3f883d0d_d051ff89_81f75280_3dfc0553_34815488_5675883d_748338dc;
+defparam bootram.RAM4.INIT_2D=256'h81ff0670_e63f8008_705256d0_02a70533_3dfc0552_34815389_0533893d_7c5702ab;
+defparam bootram.RAM4.INIT_2E=256'h5473802e_ff067056_3f800881_7551cfa9_76537b52_77259738_2e9e3880_56547380;
+defparam bootram.RAM4.INIT_2F=256'ha03f800b_80d051ff_5381f752_883dfc05_3d0d8154_3d0d04fa_74800c89_83388155;
+defparam bootram.RAM4.INIT_30=256'h0c80eb0b_0b81c094_3d0d0499_75800c88_83388156_2e098106_567480de_883d3356;
+defparam bootram.RAM4.INIT_31=256'h810781c0_be800670_0d72882b_0c04803d_0b81c0b0_ac0c89b0_a60b81c0_81c0800c;
+defparam bootram.RAM4.INIT_32=256'h08800c82_3881c0a8_515170f1_70810651_0870812a_0c81c0a4_0b81c0a0_980c5182;
+defparam bootram.RAM4.INIT_33=256'hc0a00c81_0c840b81_7381c09c_c0980c51_70810781_2bbe8006_3d0d7288_3d0d0480;
+defparam bootram.RAM4.INIT_34=256'h83065555_787a7c72_39fa3d0d_3d0d04ff_70f13882_06515151_812a7081_c0a40870;
+defparam bootram.RAM4.INIT_35=256'h2a725555_f93f7282_38815188_71802e86_72830652_52718a38_38758306_57577191;
+defparam bootram.RAM4.INIT_36=256'hfe3d0d74_883d0d04_1454e939_52545281_7008720c_77117712_3873822b_73752794;
+defparam bootram.RAM4.INIT_37=256'hcaa83f84_11335253_0680ecc4_b53f728f_515353ca_c4113354_8f0680ec_70842a70;
+defparam bootram.RAM4.INIT_38=256'h0d029305_0d04fe3d_f138823d_51515170_2a708106_90087088_3d0d82e0_3d0d0480;
+defparam bootram.RAM4.INIT_39=256'h5170f138_81065151_70882a70_82e09008_80075353_060780c0_067a8c80_337880ff;
+defparam bootram.RAM4.INIT_3A=256'h72802e96_900c7251_800782e0_980c7182_ff0682e0_900c7581_0c7182e0_7682e080;
+defparam bootram.RAM4.INIT_3B=256'h04fc3d0d_0c843d0d_08517080_3882e080_515170f1_70810651_0870882a_3882e090;
+defparam bootram.RAM4.INIT_3C=256'h80559054_fc3d0d88_863d0d04_51ff873f_53805280_55885480_940c8880_810b82e0;
+defparam bootram.RAM4.INIT_3D=256'h54865381_88805588_04fc3d0d_0c863d0d_81ff0680_f13f8008_528151fe_8a805381;
+defparam bootram.RAM4.INIT_3E=256'h3d0deb3f_3d0d0480_06800c82_08813281_0dca3f80_0d04803d_d53f863d_528051fe;
+defparam bootram.RAM4.INIT_3F=256'h38dd3fff_8008269b_85923f75_3d0d7756_3d0d04fb_2ef43882_06517080_800881ff;
+defparam bootram.RAM5.INIT_00=256'hba3d0d80_3d0d04ff_fe843f87_81528051_9b0a0753_fe9b0a06_55a05475_b43f8880;
+defparam bootram.RAM5.INIT_01=256'h80082681_84ce3f73_38751754_ff2681b4_80557381_11565757_cb3d08ff_c93d0880;
+defparam bootram.RAM5.INIT_02=256'hfefd3ffe_518b993f_3d085273_755380cb_548cbe3f_883d7052_5381ff52_a7388280;
+defparam bootram.RAM5.INIT_03=256'h800c810b_0a0782e0_0a0680c0_0c76fec0_0b82e090_980c8880_3f7482e0_d43ffd9f;
+defparam bootram.RAM5.INIT_04=256'h80157008_558f56fe_3f80c83d_900cfcef_a00b82e0_e0900c8a_88a00b82_82e0980c;
+defparam bootram.RAM5.INIT_05=256'h700882e0_54fe8c15_82e0840c_88157008_880c54fe_700882e0_54fe8415_82e08c0c;
+defparam bootram.RAM5.INIT_06=256'h25ffbc38_56567580_ff169016_0cfcb03f_0b82e090_900c8a80_800b82e0_800c5488;
+defparam bootram.RAM5.INIT_07=256'h838a3f80_575a5656_7b7d7212_f93d0d79_c83d0d04_74800c80_980c8155_800b82e0;
+defparam bootram.RAM5.INIT_08=256'h74317555_a2388280_5473802e_7581ff06_2e80c338_81577480_2680cb38_57738008;
+defparam bootram.RAM5.INIT_09=256'h802e8e38_57595674_19767631_3f731674_7551fdeb_77537352_83387654_57767527;
+defparam bootram.RAM5.INIT_0A=256'h76787a56_04fc3d0d_0c893d0d_81577680_39fd8c3f_828054dc_7527e138_74548280;
+defparam bootram.RAM5.INIT_0B=256'h0c80750c_800b8416_0b88160c_27903880_3f800874_1354829c_2e8d3873_54557380;
+defparam bootram.RAM5.INIT_0C=256'h160c7188_0c740684_08307276_81ec3f80_16565152_707406ff_3f800830_a63981fa;
+defparam bootram.RAM5.INIT_0D=256'h802e9f38_70545271_0881ff06_fc983f80_3d0d7554_3d0d04fd_fcc93f86_160c7151;
+defparam bootram.RAM5.INIT_0E=256'h80537280_51fc943f_7088160c_08800805_b13f8814_2e943881_08841508_81538814;
+defparam bootram.RAM5.INIT_0F=256'h0a06800c_8008fe80_51faa33f_53815281_5481f90a_888055a0_04fc3d0d_0c853d0d;
+defparam bootram.RAM5.INIT_10=256'h81ff0670_ff068008_882a7081_d43f8008_7480c238_f99c0855_fb3d0d80_863d0d04;
+defparam bootram.RAM5.INIT_11=256'h06547380_93387481_7380c02e_83388155_3f73a02e_5154cdff_ecd45458_56715580;
+defparam bootram.RAM5.INIT_12=256'h8d387452_55827427_08ea1155_0c80f99c_7580f99c_a93f9c39_ecec51c4_2e8a3880;
+defparam bootram.RAM5.INIT_13=256'h0c04f23f_f6053380_800880ed_04ff913f_0c873d0d_a93f7480_cdc53ff5_80ed8c51;
+defparam bootram.RAM5.INIT_14=256'h0b82e098_f8e93f80_3d0d7d56_800c04f6_0b80082b_fefa3f81_2b800c04_810b8008;
+defparam bootram.RAM5.INIT_15=256'ha80b82e0_e0980c88_0c810b82_2b82e080_840c7c88_8b0b82e0_82e0900c_0c88800b;
+defparam bootram.RAM5.INIT_16=256'h0c8a800b_0b82e090_d3388880_73762780_7e558054_0cf8b83f_0b82e090_900c8aa8;
+defparam bootram.RAM5.INIT_17=256'h3d767531_80085b88_085a82e0_5982e084_82e08808_e08c0858_f89d3f82_82e0900c;
+defparam bootram.RAM5.INIT_18=256'h34811252_70810557_51703375_91387117_52717327_38705380_70732783_52579053;
+defparam bootram.RAM5.INIT_19=256'h028c0cfd_da3f8c08_0d7251f6_0d04803d_980c8c3d_800b82e0_54ffa939_ec397214;
+defparam bootram.RAM5.INIT_1A=256'h8c0c048c_54853d0d_0870800c_82de3f80_88050851_08528c08_8c088c05_3d0d8053;
+defparam bootram.RAM5.INIT_1B=256'h0c54853d_80087080_5182b93f_08880508_0508528c_538c088c_fd3d0d81_08028c0c;
+defparam bootram.RAM5.INIT_1C=256'h8c088805_8025ab38_08880508_fc050c8c_800b8c08_0cf93d0d_8c08028c_0d8c0c04;
+defparam bootram.RAM5.INIT_1D=256'h8c08f405_08f4050c_38810b8c_fc050888_050c8c08_0b8c08f4_88050c80_08308c08;
+defparam bootram.RAM5.INIT_1E=256'h8c08f005_050c800b_308c088c_088c0508_25ab388c_8c050880_050c8c08_088c08fc;
+defparam bootram.RAM5.INIT_1F=256'h088c0508_0c80538c_8c08fc05_08f00508_f0050c8c_810b8c08_05088838_0c8c08fc;
+defparam bootram.RAM5.INIT_20=256'h8c08f805_802e8c38_08fc0508_050c548c_708c08f8_a73f8008_05085181_528c0888;
+defparam bootram.RAM5.INIT_21=256'h3d0d800b_028c0cfb_0c048c08_893d0d8c_70800c54_08f80508_f8050c8c_08308c08;
+defparam bootram.RAM5.INIT_22=256'h08fc050c_0c810b8c_8c088805_88050830_93388c08_05088025_0c8c0888_8c08fc05;
+defparam bootram.RAM5.INIT_23=256'h8c088805_8c050852_81538c08_088c050c_0508308c_388c088c_0880258c_8c088c05;
+defparam bootram.RAM5.INIT_24=256'h8c08f805_f8050830_8c388c08_0508802e_548c08fc_08f8050c_8008708c_0851ad3f;
+defparam bootram.RAM5.INIT_25=256'hfc050c80_810b8c08_0cfd3d0d_8c08028c_0d8c0c04_0c54873d_05087080_0c8c08f8;
+defparam bootram.RAM5.INIT_26=256'h800b8c08_802ea338_08fc0508_27ac388c_08880508_8c05088c_050c8c08_0b8c08f8;
+defparam bootram.RAM5.INIT_27=256'hc9398c08_08fc050c_0508108c_0c8c08fc_8c088c05_8c050810_99388c08_8c050824;
+defparam bootram.RAM5.INIT_28=256'h8c050831_05088c08_388c0888_050826a1_088c0888_8c088c05_2e80c938_fc050880;
+defparam bootram.RAM5.INIT_29=256'h8c08fc05_0508812a_0c8c08fc_8c08f805_fc050807_05088c08_0c8c08f8_8c088805;
+defparam bootram.RAM5.INIT_2A=256'h0508708c_388c0888_08802e8f_8c089005_0cffaf39_8c088c05_0508812a_0c8c088c;
+defparam bootram.RAM5.INIT_2B=256'h0d8c0c04_800c853d_08f40508_050c518c_708c08f4_08f80508_518d398c_08f4050c;
+defparam bootram.RAM5.INIT_2C=256'h71ff2ea0_38ff1252_70802eb0_07830651_8c387474_52837227_77795656_fc3d0d78;
+defparam bootram.RAM5.INIT_2D=256'h8106e238_71ff2e09_14545555_158115ff_06bd3881_712e0981_33525372_38743374;
+defparam bootram.RAM5.INIT_2E=256'h54545171_8414fc14_8f388411_2e098106_70087308_74745451_863d0d04_800b800c;
+defparam bootram.RAM5.INIT_2F=256'h5555558f_70797b55_fc3d0d76_863d0d04_7131800c_ffaf3972_70735555_8326e938;
+defparam bootram.RAM5.INIT_30=256'h33747081_70810554_2e983872_125271ff_2ea738ff_06517080_72750783_72278c38;
+defparam bootram.RAM5.INIT_31=256'h08717084_70840554_04745172_0c863d0d_ea387480_2e098106_125271ff_055634ff;
+defparam bootram.RAM5.INIT_32=256'h70840554_05530c72_08717084_70840554_05530c72_08717084_70840554_05530c72;
+defparam bootram.RAM5.INIT_33=256'h8405530c_54087170_72708405_72279538_26c93883_1252718f_05530cf0_08717084;
+defparam bootram.RAM5.INIT_34=256'h55837227_33575553_8c059f05_76797102_39fc3d0d_7054ff83_8326ed38_fc125271;
+defparam bootram.RAM5.INIT_35=256'h5271ff2e_5534ff12_73708105_2e933873_125271ff_2ea238ff_06517080_8a387483;
+defparam bootram.RAM5.INIT_36=256'h27a53872_54518f72_902b0751_75077071_7474882b_863d0d04_3874800c_098106ef;
+defparam bootram.RAM5.INIT_37=256'h1252718f_05530cf0_72717084_8405530c_0c727170_70840553_530c7271_71708405;
+defparam bootram.RAM5.INIT_38=256'hfa3d0d78_53ff9039_26f23870_12527183_05530cfc_72717084_72279038_26dd3883;
+defparam bootram.RAM5.INIT_39=256'h72ff2eb1_38ff1353_802e80d4_83065170_38717407_802e80d9_55555272_7a7c7054;
+defparam bootram.RAM5.INIT_3A=256'h2e80fc38_06517080_387081ff_802e8187_06a93872_712e0981_33565174_38713374;
+defparam bootram.RAM5.INIT_3B=256'h81ff0671_81ff0675_33565170_38713374_098106d1_5272ff2e_ff155555_81128115;
+defparam bootram.RAM5.INIT_3C=256'h74765552_082e8838_38710874_83732788_71745755_883d0d04_5270800c_71315152;
+defparam bootram.RAM5.INIT_3D=256'h51515170_82818006_0670f884_fbfdff12_087009f7_2eb13874_13537280_ff9739fc;
+defparam bootram.RAM5.INIT_3E=256'h0b800c88_fedf3980_74765552_082ed038_38740876_837327d0_84175755_9a388415;
+defparam bootram.RAM5.INIT_3F=256'hffa8813f_ffa8e53f_80f9a00c_2e9e3873_54547281_80edcc08_3d0d800b_3d0d04fd;
+defparam bootram.RAM6.INIT_00=256'h3f80ee90_3fffa7e4_0cffa8c8_7280f9a0_51f6a33f_8c3f8008_8151ffb1_80ee9052;
+defparam bootram.RAM6.INIT_01=256'h5270ff2e_05700852_ee980bfc_ff3d0d80_3f00ff39_0851f686_b0ef3f80_528151ff;
+defparam bootram.RAM6.INIT_02=256'h00000040_a8f33f04_0d0404ff_f138833d_2e098106_525270ff_fc127008_9138702d;
+defparam bootram.RAM6.INIT_03=256'h646c6572_2068616e_636b6574_6c207061_6e74726f_6e20636f_6f722069_21457272;
+defparam bootram.RAM6.INIT_04=256'h62657220_206e756d_6c697479_74696269_6f6d7061_65642063_70656374_3a204578;
+defparam bootram.RAM6.INIT_05=256'h6e74726f_6e20636f_6f722069_21457272_25640a00_676f7420_62757420_25642c20;
+defparam bootram.RAM6.INIT_06=256'h61796c6f_65642070_70656374_3a204578_646c6572_2068616e_636b6574_6c207061;
+defparam bootram.RAM6.INIT_07=256'h53504920_0a000000_74202564_7420676f_2c206275_68202564_656e6774_6164206c;
+defparam bootram.RAM6.INIT_08=256'h206e756d_30782578_61746120_25642064_64657620_20746f20_73616374_7472616e;
+defparam bootram.RAM6.INIT_09=256'h643a2073_616e6765_6b206368_206c696e_0a657468_0a000000_73202564_5f626974;
+defparam bootram.RAM6.INIT_0A=256'h6f6f746c_44502062_31302055_50204e32_0a555352_640a0000_203d2025_70656564;
+defparam bootram.RAM6.INIT_0B=256'h756d6265_7479206e_62696c69_70617469_20636f6d_46504741_720a0000_6f616465;
+defparam bootram.RAM6.INIT_0C=256'h7479206e_62696c69_70617469_20636f6d_77617265_4669726d_640a0000_723a2025;
+defparam bootram.RAM6.INIT_0D=256'h65636f76_69702072_476f7420_00000000_61646472_640a0000_723a2025_756d6265;
+defparam bootram.RAM6.INIT_0E=256'h00000820_00000820_00000770_00000787_00000000_65743a20_7061636b_65727920;
+defparam bootram.RAM6.INIT_0F=256'h000006ee_000007a4_00000820_00000820_00000820_00000820_00000820_000007f6;
+defparam bootram.RAM6.INIT_10=256'h000007bf_000006c1_00000820_00000820_00000820_00000820_000006b4_00000820;
+defparam bootram.RAM6.INIT_11=256'h70207665_20636869_4c4d5331_000007e4_000007d7_000007d0_000007c9_000007c4;
+defparam bootram.RAM6.INIT_12=256'h7273696f_70207665_20636869_4c4d5332_0a000000_30782578_6e203d20_7273696f;
+defparam bootram.RAM6.INIT_13=256'h054a0387_15290a94_3fff0000_0050c285_c0a80a02_0a000000_30782578_6e203d20;
+defparam bootram.RAM6.INIT_14=256'h38394142_34353637_30313233_2e256400_642e2564_25642e25_45000000_01c300e2;
+defparam bootram.RAM6.INIT_15=256'h6420616c_3a206261_5f706b74_73656e64_ffff0000_ffffffff_00000000_43444546;
+defparam bootram.RAM6.INIT_16=256'h6e65745f_66000000_72206275_6e642f6f_656e2061_6f66206c_656e7420_69676e6d;
+defparam bootram.RAM6.INIT_17=256'h6c6f6f6b_63686520_74206361_6f206869_65642074_6661696c_6f6e3a20_636f6d6d;
+defparam bootram.RAM6.INIT_18=256'h72642073_20776569_6172703a_646c655f_0a68616e_00000000_666f7220_696e6720;
+defparam bootram.RAM6.INIT_19=256'h206c656e_74656e74_6e736973_696e636f_55445020_0a000000_3d202564_697a6520;
+defparam bootram.RAM6.INIT_1A=256'h6f6e2069_75637469_50726f64_0b0b0b0b_00000000_2025640a_3a202564_67746873;
+defparam bootram.RAM6.INIT_1B=256'h696e2073_50322b20_20555352_74696e67_53746172_640a0000_203d2025_6d616765;
+defparam bootram.RAM6.INIT_1C=256'h6172652e_69726d77_66652066_67207361_6164696e_2e204c6f_6d6f6465_61666520;
+defparam bootram.RAM6.INIT_1D=256'h6374696f_726f6475_69642070_2076616c_20666f72_6b696e67_43686563_00000000;
+defparam bootram.RAM6.INIT_1E=256'h74696f6e_6f647563_64207072_56616c69_2e2e2e00_6d616765_47412069_6e204650;
+defparam bootram.RAM6.INIT_1F=256'h6720746f_7074696e_7474656d_642e2041_666f756e_61676520_4120696d_20465047;
+defparam bootram.RAM6.INIT_20=256'h46504741_696f6e20_64756374_2070726f_616c6964_4e6f2076_742e0000_20626f6f;
+defparam bootram.RAM6.INIT_21=256'h74696f6e_6f647563_64207072_56616c69_2e0a0000_6f756e64_67652066_20696d61;
+defparam bootram.RAM6.INIT_22=256'h46696e69_2e2e2e00_64696e67_204c6f61_756e642e_6520666f_6d776172_20666972;
+defparam bootram.RAM6.INIT_23=256'h2e000000_6d616765_6e672069_61727469_2e205374_64696e67_206c6f61_73686564;
+defparam bootram.RAM6.INIT_24=256'h72616d21_70726f67_61696e20_6f6d206d_6e206672_65747572_523a2052_4552524f;
+defparam bootram.RAM6.INIT_25=256'h4e6f2076_6e210000_61707065_65722068_206e6576_6f756c64_73207368_20546869;
+defparam bootram.RAM6.INIT_26=256'h6e642e20_20666f75_77617265_6669726d_696f6e20_64756374_2070726f_616c6964;
+defparam bootram.RAM6.INIT_27=256'h6669726d_2d696e20_75696c74_746f2062_75676820_7468726f_696e6720_46616c6c;
+defparam bootram.RAM6.INIT_28=256'h4e4f4e45_00000000_2025640a_7420746f_64207365_53706565_2e000000_77617265;
+defparam bootram.RAM6.INIT_29=256'h43000000_45545249_53594d4d_58000000_57455f52_58000000_57455f54_00000000;
+defparam bootram.RAM6.INIT_2A=256'h4155544f_5048595f_6c3a2000_6e74726f_7720636f_20666c6f_726e6574_65746865;
+defparam bootram.RAM6.INIT_2B=256'h780a0000_20307825_20676f74_7825782c_74652030_2077726f_4144563a_4e45475f;
+defparam bootram.RAM6.INIT_2C=256'h64617465_6e207570_6f722069_21457272_00030203_00000001_00030003_00000000;
+defparam bootram.RAM6.INIT_2D=256'h796c6f61_64207061_65637465_20457870_6c65723a_68616e64_6b657420_20706163;
+defparam bootram.RAM6.INIT_2E=256'h00002417_00000000_2025640a_20676f74_20627574_2025642c_6e677468_64206c65;
+defparam bootram.RAM6.INIT_2F=256'h000024df_000024df_000024df_00002456_00002478_0000248d_000024df_000024df;
+defparam bootram.RAM6.INIT_30=256'h000024df_000024df_000024df_000024df_000024df_000024df_000024df_000024df;
+defparam bootram.RAM6.INIT_31=256'h6f72740a_0a0a6162_000024a9_00002468_000024df_000024df_000024d3_000024bc;
+defparam bootram.RAM6.INIT_32=256'h7970653d_73682074_0a666c61_43444546_38394142_34353637_30313233_00000000;
+defparam bootram.RAM6.INIT_33=256'h652e2041_20747970_6c617368_6e672066_0a57726f_25640a00_697a653d_25642073;
+defparam bootram.RAM6.INIT_34=256'h653a2025_2073697a_6c617368_6e672066_0a57726f_00000000_6e67210a_63687475;
+defparam bootram.RAM6.INIT_35=256'hff00ffff_00ffffff_65000000_792e6578_64756d6d_67210a00_6874756e_64204163;
+defparam bootram.RAM6.INIT_36=256'h0050c285_c0a80a02_00003720_00000000_00000000_00000000_ffffff00_ffff00ff;
+defparam bootram.RAM6.INIT_37=256'h0000351c_03197500_000c0000_00190010_ffff0033_05050000_01010100_3fff0000;
+defparam bootram.RAM6.INIT_38=256'hffffffff_00000000_ffffffff_000036ac_10101200_00003534_0000352c_00003524;
 defparam bootram.RAM6.INIT_39=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
 defparam bootram.RAM6.INIT_3A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
 defparam bootram.RAM6.INIT_3B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
--- a/fpga/usrp2/top/N2x0/u2plus_core.v
+++ b/fpga/usrp2/top/N2x0/u2plus_core.v
@@ -216,25 +216,33 @@ module u2plus_core
   localparam SR_RX_FRONT0 =  20;   // 5
   localparam SR_RX_FRONT1 =  25;   // 5
 `endif // !`ifndef LMS602D_FRONTEND
-   localparam SR_RX_CTRL0 =  32;   // 9
-   localparam SR_RX_DSP0  =  48;   // 7
-   localparam SR_RX_CTRL1 =  80;   // 9
-   localparam SR_RX_DSP1  =  96;   // 7
+   localparam SR_RX_CTRL0 =  32;   // 10
+   localparam SR_RX_DSP0  =  42;   // 7
+   localparam SR_RX_CTRL1 =  49;   // 10
+   localparam SR_RX_DSP1  =  59;   // 7
+
+   // RX DSP registers for lms0
+   localparam SR_RX_CTRL0_2 =  66;   // 10
+   localparam SR_RX_DSP0_2  =  76;   // 7
+
+   localparam SR_RX_CTRL0_3 =  83;   // 10
+   localparam SR_RX_DSP0_3  =  93;   // 7
+
+   localparam SR_RX_CTRL0_4 =  100;   // 10
+   localparam SR_RX_DSP0_4  =  110;   // 7
+
+   // RX DSP registers for lms1
+   localparam SR_RX_CTRL1_2 =  117;   // 10
+   localparam SR_RX_DSP1_2  =  127;   // 7
+
+   localparam SR_RX_CTRL1_3 =  134;   // 10
+   localparam SR_RX_DSP1_3  =  144;   // 7
+
+   localparam SR_RX_CTRL1_4 =  151;   // 10
+   localparam SR_RX_DSP1_4  =  161;   // 7

-`ifndef LMS602D_FRONTEND
-   localparam SR_TX_FRONT = 128;   // ?
-   localparam SR_TX_CTRL  = 144;   // 6
-   localparam SR_TX_DSP   = 160;   // 5
-`else
-   localparam SR_TX_FRONT = 110;   // ?
-   localparam SR_TX_CTRL  = 126;   // 6
-   localparam SR_TX_DSP   = 135;   // 5
-   localparam SR_TX1_FRONT = 145;   // ?
-   localparam SR_TX1_CTRL  = 161;   // 6
-   localparam SR_TX1_DSP   = 170;   // 5
   localparam SR_RX_FRONT_SW = 176;
   localparam SR_TX_FRONT_SW = 177;
-`endif // !`ifndef LMS602D_FRONTEND

   localparam SR_DIVSW    = 180;   // 2
   localparam SR_GPIO     = 184;   // 5   
@@ -283,7 +291,12 @@ module u2plus_core
   wire 	 run_tx1;
   wire   run_tx0_mux, run_tx1_mux;
 `endif // !`ifdef LMS602D_FRONTEND
+   wire 	 run_rx0_2, run_rx0_3, run_rx0_4;
+   wire 	 run_rx1_2, run_rx1_3, run_rx1_4;
   reg 		 run_rx0_d1, run_rx1_d1;
+   reg 		 run_rx0_d2, run_rx1_d2;
+   reg 		 run_rx0_d3, run_rx1_d3;
+   reg 		 run_rx0_d4, run_rx1_d4;
   
   // ///////////////////////////////////////////////////////////////////////////////////////////////
   // Wishbone Single Master INTERCON
@@ -459,6 +472,10 @@ module u2plus_core
   wire 	 wr3_ready_i, wr3_ready_o;
   wire [35:0] 	 wr0_dat, wr1_dat, wr2_dat, wr3_dat;

+   wire [35:0] 	 wr4_dat, wr5_dat;
+   wire 	 wr4_ready_i, wr4_ready_o;
+   wire 	 wr5_ready_i, wr5_ready_o;
+
   wire [35:0] 	 tx_err_data;
   wire 	 tx_err_src_rdy, tx_err_dst_rdy;
 `ifdef LMS602D_FRONTEND
@@ -482,14 +499,13 @@ module u2plus_core
      .ser_inp_data(wr0_dat), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o),
      .dsp0_inp_data(wr1_dat), .dsp0_inp_valid(wr1_ready_i), .dsp0_inp_ready(wr1_ready_o),
      .dsp1_inp_data(wr3_dat), .dsp1_inp_valid(wr3_ready_i), .dsp1_inp_ready(wr3_ready_o),
+      .dsp2_inp_data(wr4_dat), .dsp2_inp_valid(wr4_ready_i), .dsp2_inp_ready(wr4_ready_o),
+      .dsp3_inp_data(wr5_dat), .dsp3_inp_valid(wr5_ready_i), .dsp3_inp_ready(wr5_ready_o),
      .eth_inp_data(wr2_dat), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o),
-      .err_inp_data(tx_err_data), .err_inp_ready(tx_err_dst_rdy), .err_inp_valid(tx_err_src_rdy),
-
      .ser_out_data(rd0_dat), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i),
-      .dsp_out_data(rd1_dat), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i),
+      .dsp_out_data(), .dsp_out_valid(), .dsp_out_ready(),
 `ifdef LMS602D_FRONTEND
-      .dsp1_out_valid(rd1_ready_o_1), .dsp1_out_ready(rd1_ready_i_1),
-      .err_inp1_data(tx1_err_data), .err_inp1_ready(tx1_err_dst_rdy), .err_inp1_valid(tx1_err_src_rdy),
+      .dsp1_out_valid(), .dsp1_out_ready(),
 `endif // !`ifdef LMS602D_FRONTEND
      .eth_out_data(rd2_dat), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i)
      );
@@ -644,7 +660,7 @@ module u2plus_core
 `ifndef LMS602D_FRONTEND
   wire [7:0] 	 led_hw = {run_tx, (run_rx0_d1 | run_rx1_d1), clk_status, serdes_link_up & good_sync, 1'b0};
 `else
-   wire [7:0] 	 led_hw = {run_tx0_mux, run_rx0_mux, run_tx1_mux, run_rx1_mux, 1'b0};
+   wire [7:0] 	 led_hw = {run_rx2_mux, run_rx0_mux, run_rx3_mux, run_rx1_mux, 1'b0};
 `endif // !`ifndef LMS602D_FRONTEND
   
   setting_reg #(.my_addr(SR_MISC+3),.width(8)) sr_led
@@ -734,8 +750,11 @@ module u2plus_core
 `else
   wire [23:0] 	 adc_i_0, adc_q_0, adc_i_1, adc_q_1;
   wire [23:0] 	 i_0_mux, q_0_mux, i_1_mux, q_1_mux;
+   wire [23:0] 	 i_2_mux, q_2_mux, i_3_mux, q_3_mux;
   wire run_rx0_mux, run_rx1_mux;
+   wire run_rx2_mux, run_rx3_mux;
   wire adc_ovf_i_0_mux, adc_ovf_q_0_mux, adc_ovf_i_1_mux, adc_ovf_q_1_mux;
+   wire adc_ovf_i_2_mux, adc_ovf_q_2_mux, adc_ovf_i_3_mux, adc_ovf_q_3_mux;
   
   rx_frontend #(.BASE(SR_RX_FRONT0)) rx_frontend0
     (.clk(dsp_clk),.rst(dsp_rst),
@@ -760,13 +779,19 @@ module u2plus_core
      .i_0_in(adc_i_0), .q_0_in(adc_q_0), 
      .i_1_in(adc_i_1), .q_1_in(adc_q_1), 
      .run_0_in(run_rx0_d1), .run_1_in(run_rx1_d1), 
+      .run_2_in(run_rx0_d2), .run_3_in(run_rx1_d2), 
      .adc_ovf_i_0_in(adc_ovf_a_0), .adc_ovf_q_0_in(adc_ovf_b_0), 
      .adc_ovf_i_1_in(adc_ovf_a_1), .adc_ovf_q_1_in(adc_ovf_b_1), 
      .i_0_mux(i_0_mux), .q_0_mux(q_0_mux), 
-      .i_1_mux(i_1_mux), .q_1_mux(q_1_mux), 
+      .i_1_mux(i_1_mux), .q_1_mux(q_1_mux),
+      .i_2_mux(i_2_mux), .q_2_mux(q_2_mux), 
+      .i_3_mux(i_3_mux), .q_3_mux(q_3_mux),
      .run_0_mux(run_rx0_mux), .run_1_mux(run_rx1_mux), 
+      .run_2_mux(run_rx2_mux), .run_3_mux(run_rx3_mux),
      .adc_ovf_i_0_mux(adc_ovf_i_0_mux), .adc_ovf_q_0_mux(adc_ovf_q_0_mux), 
-      .adc_ovf_i_1_mux(adc_ovf_i_1_mux), .adc_ovf_q_1_mux(adc_ovf_q_1_mux));      
+      .adc_ovf_i_1_mux(adc_ovf_i_1_mux), .adc_ovf_q_1_mux(adc_ovf_q_1_mux),
+      .adc_ovf_i_2_mux(adc_ovf_i_2_mux), .adc_ovf_q_2_mux(adc_ovf_q_2_mux), 
+      .adc_ovf_i_3_mux(adc_ovf_i_3_mux), .adc_ovf_q_3_mux(adc_ovf_q_3_mux));      
 `endif // !`ifndef LMS602D_FRONTEND
   
   // /////////////////////////////////////////////////////////////////////////
@@ -806,6 +831,43 @@ module u2plus_core
      .rx_data_o(wr1_dat), .rx_src_rdy_o(wr1_ready_i), .rx_dst_rdy_i(wr1_ready_o),
      .debug() );

+   // /////////////////////////////////////////////////////////////////////////
+   // DSP RX 0_2
+   wire [31:0] 	 sample_rx0_2;
+   wire 	 clear_rx0_2, strobe_rx0_2;
+
+   always @(posedge dsp_clk)
+     run_rx0_d2 <= run_rx0_2;
+   
+   dsp_core_rx #(.BASE(SR_RX_DSP0_2)) dsp_core_rx0_2
+     (.clk(dsp_clk),.rst(dsp_rst),
+`ifndef LMS_DSP
+     .adc_clk(dsp_clk),
+`else
+     .adc_clk(lms_clk),
+`endif // !`ifndef LMS_DSP
+      .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+`ifndef LMS602D_FRONTEND
+      .adc_i(adc_i),.adc_ovf_i(adc_ovf_a),.adc_q(adc_q),.adc_ovf_q(adc_ovf_b),
+`else
+      .adc_i(i_2_mux),.adc_ovf_i(adc_ovf_i_2_mux),.adc_q(q_2_mux),.adc_ovf_q(adc_ovf_q_2_mux),
+`endif // !`ifndef LMS602D_FRONTEND
+      .sample(sample_rx0_2), .run(run_rx0_d2), .strobe(strobe_rx0_2),
+      .debug() );
+
+   setting_reg #(.my_addr(SR_RX_CTRL0_2+3)) sr_clear_rx0_2
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),
+      .out(),.changed(clear_rx0_2));
+
+   vita_rx_chain #(.BASE(SR_RX_CTRL0_2),.UNIT(1),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain0_2
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx0_2),
+      .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+      .vita_time(vita_time), .overrun(),
+      .sample(sample_rx0_2), .run(run_rx0_2), .strobe(strobe_rx0_2),
+      .rx_data_o(wr4_dat), .rx_src_rdy_o(wr4_ready_i), .rx_dst_rdy_i(wr4_ready_o),
+      .debug() );
+
   // /////////////////////////////////////////////////////////////////////////
   // DSP RX 1
   wire [31:0] 	 sample_rx1;
@@ -843,163 +905,43 @@ module u2plus_core
      .rx_data_o(wr3_dat), .rx_src_rdy_o(wr3_ready_i), .rx_dst_rdy_i(wr3_ready_o),
      .debug() );

-   // ///////////////////////////////////////////////////////////////////////////////////
-   // DSP TX
-
-   wire [35:0] 	 tx_data;
-   wire 	 tx_src_rdy, tx_dst_rdy;
-`ifdef LMS602D_FRONTEND
-   wire [35:0] 	 tx_data_1;
-   wire 	 tx_src_rdy_1, tx_dst_rdy_1;
-`endif // !`ifdef LMS602D_FRONTEND
-   wire [31:0] 	 debug_vt;
-   wire 	 clear_tx;
-
-   setting_reg #(.my_addr(SR_TX_CTRL+1)) sr_clear_tx
-     (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),
-      .in(set_data_dsp),.out(),.changed(clear_tx));
-
-`ifndef NO_EXT_FIFO
-   assign 	 RAM_A[20:19] = 2'b0;
-`endif // !`ifndef NO_EXT_FIFO
-   
-   ext_fifo #(.EXT_WIDTH(36),.INT_WIDTH(36),.RAM_DEPTH(19),.FIFO_DEPTH(19)) 
-     ext_fifo_i1
-       (.int_clk(dsp_clk),
-	.ext_clk(dsp_clk),
-`ifndef LMS_DSP
-     .dac_clk(dsp_clk),
-`else
-     .dac_clk(lms_clk),
-`endif // !`ifndef LMS_DSP
-	.rst(dsp_rst | clear_tx),
-`ifndef NO_EXT_FIFO
-	.RAM_D_pi(RAM_D_pi),
-	.RAM_D_po(RAM_D_po),
-	.RAM_D_poe(RAM_D_poe),
-	.RAM_A(RAM_A[18:0]),
-	.RAM_WEn(RAM_WEn),
-	.RAM_CENn(RAM_CENn),
-	.RAM_LDn(RAM_LDn),
-	.RAM_OEn(RAM_OEn),
-	.RAM_CE1n(RAM_CE1n),
-`else
-	.RAM_D_pi(),
-	.RAM_D_po(),
-	.RAM_D_poe(),
-	.RAM_A(),
-	.RAM_WEn(),
-	.RAM_CENn(),
-	.RAM_LDn(),
-	.RAM_OEn(),
-	.RAM_CE1n(),
-`endif // !`ifndef NO_EXT_FIFO
-	.datain(rd1_dat),
-	.src_rdy_i(rd1_ready_o),
-	.dst_rdy_o(rd1_ready_i),
-	.dataout(tx_data),
-	.src_rdy_o(tx_src_rdy),
-	.dst_rdy_i(tx_dst_rdy),
-`ifdef LMS602D_FRONTEND
-	.src1_rdy_i(rd1_ready_o_1),
-	.dst1_rdy_o(rd1_ready_i_1),
-	.src1_rdy_o(tx_src_rdy_1),
-	.dst1_rdy_i(tx_dst_rdy_1),
-	.dataout_1(tx_data_1),
-`endif // !`ifdef LMS602D_FRONTEND
-	.debug(debug_extfifo),
-	.debug2(debug_extfifo2) );
-
   // /////////////////////////////////////////////////////////////////////////
-   // DSP TX 0
-   wire [23:0] 	 tx_i, tx_q;
-   wire [23:0] 	 tx1_i, tx1_q;
-   wire [23:0] 	 front_i_0, front_q_0;
-   wire [23:0] 	 front_i_1, front_q_1;
-   
-   vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), 
-		   .REPORT_ERROR(1), .DO_FLOW_CONTROL(1),
-		   .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1),
-		   .DSP_NUMBER(0))
-   vita_tx_chain
-     (.clk(dsp_clk), .reset(dsp_rst),
-`ifndef LMS_DSP
-     .dac_clk(dsp_clk),
-      .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
-`else
-     .dac_clk(lms_clk),
-      .set_stb(set_stb_dsp_low),.set_addr(set_addr_dsp_low),.set_data(set_data_dsp_low),
-`endif // !`ifndef LMS_DSP
-      .vita_time(vita_time),
-      .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
-      .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
-      .tx_i(tx_i),.tx_q(tx_q),
-      .underrun(underrun), .run(run_tx),
-      .debug(debug_vt));
+   // DSP RX 1_2
+   wire [31:0] 	 sample_rx1_2;
+   wire 	 clear_rx1_2, strobe_rx1_2;

-`ifdef LMS602D_FRONTEND     
-   frontend_sw #(.BASE(SR_TX_FRONT_SW)) tx_frontend_sw
-     (
-      .clk(lms_clk), .rst(dsp_rst),
-      .set_stb(set_stb_dsp_low),.set_addr(set_addr_dsp_low),.set_data(set_data_dsp_low),
-      .i_0_in(tx_i), .q_0_in(tx_q), 
-      .i_1_in(tx1_i), .q_1_in(tx1_q),
-      .i_0_mux(front_i_0), .q_0_mux(front_q_0), 
-      .i_1_mux(front_i_1), .q_1_mux(front_q_1),
-      .run_0_in(run_tx), .run_1_in(run_tx1),       
-      .run_0_mux(run_tx0_mux), .run_1_mux(run_tx1_mux),      
-      .adc_ovf_i_0_in(), .adc_ovf_q_0_in(), 
-      .adc_ovf_i_1_in(), .adc_ovf_q_1_in(),  
-      .adc_ovf_i_0_mux(), .adc_ovf_q_0_mux(), 
-      .adc_ovf_i_1_mux(), .adc_ovf_q_1_mux());  
+   always @(posedge dsp_clk)
+     run_rx1_d2 <= run_rx1_2;
+   
+   dsp_core_rx #(.BASE(SR_RX_DSP1_2)) dsp_core_rx1_2
+     (.clk(dsp_clk),.rst(dsp_rst),
+`ifndef LMS_DSP
+     .adc_clk(dsp_clk),
+`else
+     .adc_clk(lms_clk),
+`endif // !`ifndef LMS_DSP
+      .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+`ifndef LMS602D_FRONTEND
+      .adc_i(adc_i),.adc_ovf_i(adc_ovf_a),.adc_q(adc_q),.adc_ovf_q(adc_ovf_b),
+`else
+      .adc_i(i_3_mux),.adc_ovf_i(adc_ovf_i_3_mux),.adc_q(q_3_mux),.adc_ovf_q(adc_ovf_q_3_mux),
 `endif // !`ifndef LMS602D_FRONTEND
+      .sample(sample_rx1_2), .run(run_rx1_d2), .strobe(strobe_rx1_2),
+      .debug() );

-   tx_frontend #(.BASE(SR_TX_FRONT)) tx_frontend
-     (
-`ifndef LMS_DSP
-     .clk(dsp_clk), .rst(dsp_rst),
-      .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
-`else
-     .clk(lms_clk), .rst(dsp_rst),
-      .set_stb(set_stb_dsp_low),.set_addr(set_addr_dsp_low),.set_data(set_data_dsp_low),
-`endif // !`ifndef LMS_DSP
-      .tx_i(front_i_0), .tx_q(front_q_0), .run(1'b1),
-      .dac_a(dac_a), .dac_b(dac_b));
+   setting_reg #(.my_addr(SR_RX_CTRL1_2+3)) sr_clear_rx1_2
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),
+      .out(),.changed(clear_rx1_2));

-   // /////////////////////////////////////////////////////////////////////////
-   // DSP TX 1
-   
-   vita_tx_chain #(.BASE_CTRL(SR_TX1_CTRL), .BASE_DSP(SR_TX1_DSP), 
-		   .REPORT_ERROR(1), .DO_FLOW_CONTROL(1),
-		   .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1),
-		   .DSP_NUMBER(1))
-   vita_tx1_chain
-     (.clk(dsp_clk), .reset(dsp_rst),
-`ifndef LMS_DSP
-     .dac_clk(dsp_clk),
+   vita_rx_chain #(.BASE(SR_RX_CTRL1_2),.UNIT(3),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain1_2
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx1_2),
      .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
-`else
-     .dac_clk(lms_clk),
-      .set_stb(set_stb_dsp_low),.set_addr(set_addr_dsp_low),.set_data(set_data_dsp_low),
-`endif // !`ifndef LMS_DSP
-      .vita_time(vita_time),
-      .tx_data_i(tx_data_1), .tx_src_rdy_i(tx_src_rdy_1), .tx_dst_rdy_o(tx_dst_rdy_1),
-      .err_data_o(tx1_err_data), .err_src_rdy_o(tx1_err_src_rdy), .err_dst_rdy_i(tx1_err_dst_rdy),
-      .tx_i(tx1_i),.tx_q(tx1_q),
-      .underrun(underrun1), .run(run_tx1),
-      .debug());
+      .vita_time(vita_time), .overrun(),
+      .sample(sample_rx1_2), .run(run_rx1_2), .strobe(strobe_rx1_2),
+      .rx_data_o(wr5_dat), .rx_src_rdy_o(wr5_ready_i), .rx_dst_rdy_i(wr5_ready_o),
+      .debug() );

-   tx_frontend #(.BASE(SR_TX1_FRONT)) tx1_frontend
-     (
-`ifndef LMS_DSP
-     .clk(dsp_clk), .rst(dsp_rst),
-      .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
-`else
-     .clk(lms_clk), .rst(dsp_rst),
-      .set_stb(set_stb_dsp_low),.set_addr(set_addr_dsp_low),.set_data(set_data_dsp_low),
-`endif // !`ifndef LMS_DSP
-      .tx_i(front_i_1), .tx_q(front_q_1), .run(1'b1),
-      .dac_a(dac1_a), .dac_b(dac1_b));

   // ///////////////////////////////////////////////////////////////////////////////////
   // SERDES
--- a/fpga/usrp2/top/N2x0/u2plus_umtrx_v2.ucf
+++ b/fpga/usrp2/top/N2x0/u2plus_umtrx_v2.ucf
@@ -127,36 +127,11 @@ NET "PPS_IN" LOC = AB18;
 NET "GPS_ON" LOC = AA4; // !!!! 0-GPS_standby, 1-GPS_active.

 ## SRAM
-NET "RAM_A[0]" LOC = A14;
-NET "RAM_A[1]" LOC = C14;
-NET "RAM_A[2]" LOC = A6;
-NET "RAM_A[3]" LOC = B6;
-NET "RAM_A[4]" LOC = D3;
-NET "RAM_A[5]" LOC = D1;
-NET "RAM_A[6]" LOC = D2;
-NET "RAM_A[7]" LOC = B18;
-NET "RAM_A[8]" LOC = A18;
-NET "RAM_A[9]" LOC = C17;
-NET "RAM_A[10]" LOC = A17;
-NET "RAM_A[11]" LOC = B16;
-NET "RAM_A[12]" LOC = A16;
-NET "RAM_A[13]" LOC = C16;
-NET "RAM_A[14]" LOC = A13;
-NET "RAM_A[15]" LOC = B12;
-NET "RAM_A[16]" LOC = A12;
-NET "RAM_A[17]" LOC = A11;
-NET "RAM_A[18]" LOC = C1;// in v2 it possible the last address in ISSI 512Kx36 SRAM !!!
-NET "RAM_A[19]" LOC = A15;
-NET "RAM_A[20]" LOC = B14;
 NET "RAM_BWn[0]" LOC = C4;
 NET "RAM_BWn[1]" LOC = A4;
 NET "RAM_BWn[2]" LOC = D5; // in v1a was D7; in v2 "RAM_D[17]" LOC = D7; !!!
 NET "RAM_BWn[3]" LOC = A5;
-NET "RAM_CENn" LOC = C3;
 NET "RAM_CLK" LOC = B3;
-NET "RAM_LDn" LOC = B1;
-NET "RAM_OEn" LOC = B2;
-NET "RAM_WEn" LOC = A2;
 NET "RAM_ZZ" LOC = F16;
 NET "RAM_D[0]" LOC = E12;
 NET "RAM_D[1]" LOC = D12;
--- a/host/lib/usrp/dboard/db_lms.cpp
+++ b/host/lib/usrp/dboard/db_lms.cpp
@@ -55,6 +55,8 @@ static const std::vector<std::string> lms_tx_antennas = list_of("TX0")("TX1")("T

 static const std::vector<std::string> lms_rx_antennas = list_of("RX0")("RX1")("RX2")("RX3")("CAL");

+static const std::vector<std::string> subdevs_4xddc = list_of("0")("1")("2")("3");
+
 static const uhd::dict<std::string, gain_range_t> lms_tx_gain_ranges = map_list_of
 //    ("VGA1", gain_range_t(-35, -4, double(1.0)))
 //    ("VGA2", gain_range_t(0, 25, double(1.0)))
@@ -98,10 +100,11 @@ public:

 class db_lms6002d : public xcvr_dboard_base {
 public:
+    friend class db_lms6002d_mxddc;
    db_lms6002d(ctor_args_t args);

    double set_freq(dboard_iface::unit_t unit, double f) {
-        if (verbosity>0) printf("db_lms6002d::set_freq(%f)\n", f);
+        if (verbosity>0) printf("db_lms6002d(%s)::set_freq(%f)\n", get_subdev_name().c_str(), f);
        unsigned ref_freq = get_iface()->get_clock_rate(dboard_iface::UNIT_LMS);
        double actual_freq;
        if (unit==dboard_iface::UNIT_TX) {
@@ -130,7 +133,7 @@ public:
    }

    bool set_enabled(dboard_iface::unit_t unit, bool en) {
-        if (verbosity>0) printf("db_lms6002d::set_enabled(%d)\n", en);
+        if (verbosity>0) printf("db_lms6002d(%s)::set_enabled(%d)\n", get_subdev_name().c_str(), en);
        if (unit==dboard_iface::UNIT_RX) {
            if (en)
                lms.rx_enable();
@@ -147,7 +150,7 @@ public:
    }

    double set_rx_gain(double gain, const std::string &name) {
-        if (verbosity>0) printf("db_lms6002d::set_rx_gain(%f, %s)\n", gain, name.c_str());
+        if (verbosity>0) printf("db_lms6002d(%s)::set_rx_gain(%f, %s)\n", get_subdev_name().c_str(), gain, name.c_str());
        assert_has(lms_rx_gain_ranges.keys(), name, "LMS6002D rx gain name");
 		if(name == "VGA1"){
            lms.set_rx_vga1gain(gain);
@@ -158,14 +161,14 @@ public:
    }

    void set_rx_ant(const std::string &ant) {
-        if (verbosity>0) printf("db_lms6002d::set_rx_ant(%s)\n", ant.c_str());
+        if (verbosity>0) printf("db_lms6002d(%s)::set_rx_ant(%s)\n", get_subdev_name().c_str(), ant.c_str());
        //validate input
        assert_has(lms_rx_antennas, ant, "LMS6002D rx antenna name");

        if (ant == "CAL") {
            // Enable RF loopback if disabled
            if (!rf_loopback_enabled) {
-                if (verbosity>0) printf("db_lms6002d::set_rx_ant(%s) enabling RF loopback for LNA%d\n", ant.c_str(), lms.get_rx_lna());
+                if (verbosity>0) printf("db_lms6002d(%s)::set_rx_ant(%s) enabling RF loopback for LNA%d\n", get_subdev_name().c_str(), ant.c_str(), lms.get_rx_lna());
                lms.rf_loopback_enable(lms.get_rx_lna());
                rf_loopback_enabled = true;
            }
@@ -191,7 +194,7 @@ public:
    }

    double set_rx_bandwidth(double bandwidth) {
-        if (verbosity>0) printf("db_lms6002d::set_rx_bandwidth(%f)\n", bandwidth);
+        if (verbosity>0) printf("db_lms6002d(%s)::set_rx_bandwidth(%f)\n", get_subdev_name().c_str(), bandwidth);
        // Get the closest available bandwidth
        bandwidth = lms_bandwidth_range.clip(bandwidth);

@@ -202,7 +205,7 @@ public:
    }

    double set_tx_gain(double gain, const std::string &name) {
-        if (verbosity>0) printf("db_lms6002d::set_tx_gain(%f, %s)\n", gain, name.c_str());
+        if (verbosity>0) printf("db_lms6002d(%s)::set_tx_gain(%f, %s)\n", get_subdev_name().c_str(), gain, name.c_str());
        //validate input
        assert_has(lms_tx_gain_ranges.keys(), name, "LMS6002D tx gain name");

@@ -220,7 +223,7 @@ public:
            tx_vga1gain = int(gain) - tx_vga2gain;

            // Set the gains in hardware
-            if (verbosity>1) printf("db_lms6002d::set_tx_gain() VGA1=%d VGA2=%d\n", tx_vga1gain, tx_vga2gain);
+            if (verbosity>1) printf("db_lms6002d(%s)::set_tx_gain() VGA1=%d VGA2=%d\n", get_subdev_name().c_str(), tx_vga1gain, tx_vga2gain);
            lms.set_tx_vga1gain(tx_vga1gain);
            lms.set_tx_vga2gain(tx_vga2gain);
        } else {
@@ -232,7 +235,7 @@ public:
    }

    void set_tx_ant(const std::string &ant) {
-        if (verbosity>0) printf("db_lms6002d::set_tx_ant(%s)\n", ant.c_str());
+        if (verbosity>0) printf("db_lms6002d(%s)::set_tx_ant(%s)\n", get_subdev_name().c_str(), ant.c_str());
        //validate input
        assert_has(lms_tx_antennas, ant, "LMS6002D tx antenna ant");

@@ -251,7 +254,7 @@ public:
    }

    double set_tx_bandwidth(double bandwidth) {
-        if (verbosity>0) printf("db_lms6002d::set_tx_bandwidth(%f)\n", bandwidth);
+        if (verbosity>0) printf("db_lms6002d(%s)::set_tx_bandwidth(%f)\n", get_subdev_name().c_str(), bandwidth);
        // Get the closest available bandwidth
        bandwidth = lms_bandwidth_range.clip(bandwidth);

@@ -262,13 +265,13 @@ public:
    }

    uint8_t _set_tx_vga1dc_i_int(uint8_t offset) {
-        if (verbosity>0) printf("db_lms6002d::set_tx_vga1dc_i_int(%d)\n", offset);
+        if (verbosity>0) printf("db_lms6002d(%s)::set_tx_vga1dc_i_int(%d)\n", get_subdev_name().c_str(), offset);
        lms.set_tx_vga1dc_i_int(offset);
        return offset;
    }

    uint8_t _set_tx_vga1dc_q_int(uint8_t offset) {
-        if (verbosity>0) printf("db_lms6002d::set_tx_vga1dc_q_int(%d)\n", offset);
+        if (verbosity>0) printf("db_lms6002d(%s)::set_tx_vga1dc_q_int(%d)\n", get_subdev_name().c_str(), offset);
        lms.set_tx_vga1dc_q_int(offset);
        return offset;
    }
@@ -453,14 +456,222 @@ double db_lms6002d::tune_adf4350(double target_freq) {
    return actual_freq;
 }

+
+class db_lms6002d_mxddc : public xcvr_dboard_base {
+public:
+    typedef boost::shared_ptr<db_lms6002d>  db_lms6002d_ptr_t;
+
+    struct ifdata {
+        db_lms6002d_ptr_t ptr;
+        unsigned count;
+        unsigned enabled_mask_rx;
+        unsigned enabled_mask_tx;
+        ifdata() : count(0), enabled_mask_rx(0), enabled_mask_tx(0) {}
+    };
+
+    typedef std::map<dboard_iface*, ifdata> ifdata_storage_t;
+
+    db_lms6002d_mxddc(ctor_args_t args) : xcvr_dboard_base(args) {
+
+        ifdata& d = _ifmap[get_iface().get()];
+        if (d.ptr.get() == NULL) {
+            d.ptr.reset(new db_lms6002d(args));
+        }
+        d.count++;
+
+        _ifd = &d;
+        _db = d.ptr;
+
+        _num = atoi(get_subdev_name().c_str());
+
+        register_properties();
+
+        printf("db_lms6002d_mxddc(%s %s) iface=%p num=%d count=%d\n", get_subdev_name().c_str(), get_rx_id().to_pp_string().c_str(), get_iface().get(), _num, d.count);
+    }
+
+    ~db_lms6002d_mxddc() {
+        set_enabled(dboard_iface::UNIT_RX, false);
+        set_enabled(dboard_iface::UNIT_TX, false);
+    }
+
+    double set_freq(dboard_iface::unit_t unit, double f) {
+        if (verbosity>0) printf("db_lms6002d_mxddc(%s %p)::set_freq(%f)\n", get_subdev_name().c_str(), get_iface().get(), f);
+        return _db->set_freq(unit, f);
+    }
+
+    bool set_enabled(dboard_iface::unit_t unit, bool en) {
+        if (verbosity>0) printf("db_lms6002d_mxddc(%s %c %p)::set_enabled(%d)\n", get_subdev_name().c_str(), unit, get_iface().get(), en);
+
+        unsigned* mask = (unit == dboard_iface::UNIT_RX) ? &_ifd->enabled_mask_rx : &_ifd->enabled_mask_tx;
+        unsigned prev = *mask;
+        bool res = en;
+        if (en) {
+            *mask |= 1 << _num;
+            if (*mask && !prev) {
+                if (verbosity>0) printf("db_lms6002d_mxddc(%s)::enabling\n", get_subdev_name().c_str());
+                res = _db->set_enabled(unit, en);
+            }
+
+        } else {
+            *mask &= ~(1 << _num);
+            if (*mask == 0 && prev) {
+                if (verbosity>0) printf("db_lms6002d_mxddc(%s)::disabling\n", get_subdev_name().c_str());
+                res = _db->set_enabled(unit, en);
+            }
+        }
+        if (verbosity>0) printf("db_lms6002d_mxddc(%s %p)::mask %x\n", get_subdev_name().c_str(), get_iface().get(), *mask);
+        return res;
+    }
+
+    double set_rx_gain(double gain, const std::string &name) {
+        if (verbosity>0) printf("db_lms6002d_mxddc(%s)::set_rx_gain(%f, %s)\n", get_subdev_name().c_str(), gain, name.c_str());
+        return _db->set_rx_gain(gain, name);
+    }
+
+    void set_rx_ant(const std::string &ant) {
+        if (verbosity>0) printf("db_lms6002d_mxddc(%s)::set_rx_ant(%s)\n", get_subdev_name().c_str(), ant.c_str());
+        return _db->set_rx_ant(ant);
+    }
+
+    double set_rx_bandwidth(double bandwidth) {
+        if (verbosity>0) printf("db_lms6002d_mxddc(%s)::set_rx_bandwidth(%f)\n", get_subdev_name().c_str(), bandwidth);
+        return _db->set_rx_bandwidth(bandwidth);
+    }
+
+    double set_tx_gain(double gain, const std::string &name) {
+        if (verbosity>0) printf("db_lms6002d_mxddc(%s)::set_tx_gain(%f, %s)\n", get_subdev_name().c_str(), gain, name.c_str());
+        return _db->set_tx_gain(gain, name);
+    }
+
+    void set_tx_ant(const std::string &ant) {
+        if (verbosity>0) printf("db_lms6002d_mxddc(%s)::set_tx_ant(%s)\n", get_subdev_name().c_str(), ant.c_str());
+        return _db->set_tx_ant(ant);
+    }
+
+    double set_tx_bandwidth(double bandwidth) {
+        if (verbosity>0) printf("db_lms6002d_mxddc(%s)::set_tx_bandwidth(%f)\n", get_subdev_name().c_str(), bandwidth);
+        return _db->set_tx_bandwidth(bandwidth);
+    }
+
+    uint8_t _set_tx_vga1dc_i_int(uint8_t offset) {
+        if (verbosity>0) printf("db_lms6002d_mxddc(%s)::set_tx_vga1dc_i_int(%d)\n", get_subdev_name().c_str(), offset);
+        return _db->_set_tx_vga1dc_i_int(offset);
+    }
+
+    uint8_t _set_tx_vga1dc_q_int(uint8_t offset) {
+        if (verbosity>0) printf("db_lms6002d_mxddc(%s)::set_tx_vga1dc_q_int(%d)\n", get_subdev_name().c_str(), offset);
+        return _db->_set_tx_vga1dc_q_int(offset);
+    }
+
+    void register_properties()
+    {
+        ////////////////////////////////////////////////////////////////////
+        // Register RX properties
+        ////////////////////////////////////////////////////////////////////
+        this->get_rx_subtree()->create<std::string>("name")
+            .set(std::string(str(boost::format("%s - %s") % get_rx_id().to_pp_string() % get_subdev_name())));
+
+        BOOST_FOREACH(const std::string &name, lms_rx_gain_ranges.keys()){
+            this->get_rx_subtree()->create<double>("gains/"+name+"/value")
+                .coerce(boost::bind(&db_lms6002d_mxddc::set_rx_gain, this, _1, name))
+                .set((lms_rx_gain_ranges[name].start()+lms_rx_gain_ranges[name].stop())/2.0);
+            this->get_rx_subtree()->create<meta_range_t>("gains/"+name+"/range")
+                .set(lms_rx_gain_ranges[name]);
+        }
+
+        this->get_rx_subtree()->create<double>("freq/value")
+            .coerce(boost::bind(&db_lms6002d_mxddc::set_freq, this, dboard_iface::UNIT_RX, _1));
+        this->get_rx_subtree()->create<meta_range_t>("freq/range")
+            .set(lms_freq_range);
+
+        this->get_rx_subtree()->create<std::string>("antenna/value")
+            .subscribe(boost::bind(&db_lms6002d_mxddc::set_rx_ant, this, _1))
+            .set("RX1");
+        this->get_rx_subtree()->create<std::vector<std::string> >("antenna/options")
+            .set(lms_rx_antennas);
+        // In LMS tuning procedure doesn't finish until LO is locked, so we declare it's always locked.
+        this->get_rx_subtree()->create<sensor_value_t>("sensors/lo_locked")
+            .set(sensor_value_t("LO", true, "locked", "unlocked"));
+        this->get_rx_subtree()->create<std::string>("connection").set("IQ");
+        this->get_rx_subtree()->create<bool>("enabled")
+            .coerce(boost::bind(&db_lms6002d_mxddc::set_enabled, this, dboard_iface::UNIT_RX, _1));
+
+        this->get_rx_subtree()->create<bool>("use_lo_offset").set(false);
+        this->get_rx_subtree()->create<double>("bandwidth/value")
+            .coerce(boost::bind(&db_lms6002d_mxddc::set_rx_bandwidth, this, _1))
+            .set(double(2*0.75e6));
+        this->get_rx_subtree()->create<meta_range_t>("bandwidth/range")
+            .set(lms_bandwidth_range);
+
+        ////////////////////////////////////////////////////////////////////
+        // Register TX properties
+        ////////////////////////////////////////////////////////////////////
+        this->get_tx_subtree()->create<std::string>("name")
+            .set(std::string(str(boost::format("%s - %s") % get_tx_id().to_pp_string() % get_subdev_name())));
+
+        BOOST_FOREACH(const std::string &name, lms_tx_gain_ranges.keys()){
+            this->get_tx_subtree()->create<double>("gains/"+name+"/value")
+                .coerce(boost::bind(&db_lms6002d_mxddc::set_tx_gain, this, _1, name))
+                .set((lms_tx_gain_ranges[name].start()+lms_tx_gain_ranges[name].stop())/2.0);
+            this->get_tx_subtree()->create<meta_range_t>("gains/"+name+"/range")
+                .set(lms_tx_gain_ranges[name]);
+        }
+
+        this->get_tx_subtree()->create<double>("freq/value")
+            .coerce(boost::bind(&db_lms6002d_mxddc::set_freq, this, dboard_iface::UNIT_TX, _1));
+        this->get_tx_subtree()->create<meta_range_t>("freq/range")
+            .set(lms_freq_range);
+
+        this->get_tx_subtree()->create<std::string>("antenna/value")
+            .subscribe(boost::bind(&db_lms6002d_mxddc::set_tx_ant, this, _1))
+            .set("TX2");
+        this->get_tx_subtree()->create<std::vector<std::string> >("antenna/options")
+            .set(lms_tx_antennas);
+        // In LMS tuning procedure doesn't finish until LO is locked, so we declare it's always locked.
+        this->get_tx_subtree()->create<sensor_value_t>("sensors/lo_locked")
+            .set(sensor_value_t("LO", true, "locked", "unlocked"));
+        this->get_tx_subtree()->create<std::string>("connection").set("IQ");
+        this->get_tx_subtree()->create<bool>("enabled")
+            .coerce(boost::bind(&db_lms6002d_mxddc::set_enabled, this, dboard_iface::UNIT_TX, _1));
+
+        this->get_tx_subtree()->create<bool>("use_lo_offset").set(false);
+        this->get_tx_subtree()->create<double>("bandwidth/value")
+            .coerce(boost::bind(&db_lms6002d_mxddc::set_tx_bandwidth, this, _1))
+            .set(double(2*0.75e6));
+        this->get_tx_subtree()->create<meta_range_t>("bandwidth/range")
+            .set(lms_bandwidth_range);
+
+        // UmTRX specific calibration
+        this->get_tx_subtree()->create<uint8_t>("lms6002d/tx_dc_i/value")
+            .subscribe(boost::bind(&db_lms6002d_mxddc::_set_tx_vga1dc_i_int, this, _1))
+            .publish(boost::bind(&umtrx_lms6002d_dev::get_tx_vga1dc_i_int, &_db->lms));
+        this->get_tx_subtree()->create<uint8_t>("lms6002d/tx_dc_q/value")
+            .subscribe(boost::bind(&db_lms6002d_mxddc::_set_tx_vga1dc_q_int, this, _1))
+            .publish(boost::bind(&umtrx_lms6002d_dev::get_tx_vga1dc_q_int, &_db->lms));
+    }
+
+    db_lms6002d_ptr_t _db;
+    ifdata* _ifd;
+    unsigned _num;
+    static ifdata_storage_t _ifmap;
+};
+
+db_lms6002d_mxddc::ifdata_storage_t db_lms6002d_mxddc::_ifmap;
+
 // Register the LMS dboards

 static dboard_base::sptr make_lms6002d(dboard_base::ctor_args_t args) {
    return dboard_base::sptr(new db_lms6002d(args));
 }

+static dboard_base::sptr make_lms6002d_mxddc(dboard_base::ctor_args_t args) {
+    return dboard_base::sptr(new db_lms6002d_mxddc(args));
+}
+
+
 UHD_STATIC_BLOCK(reg_lms_dboards){
-    dboard_manager::register_dboard(0xfa07, 0xfa09, &make_lms6002d, "LMS6002D");
+    //dboard_manager::register_dboard(0xfa07, 0xfa09, &make_lms6002d, "LMS6002D");
+    dboard_manager::register_dboard(0xfa0a, 0xfa0b, &make_lms6002d_mxddc, "LMS6002D 4xDDC", subdevs_4xddc);
 }

 // LMS RX dboard configuration
@@ -487,6 +698,7 @@ db_lms6002d::db_lms6002d(ctor_args_t args) : xcvr_dboard_base(args),
    // Perform autocalibration
    lms.auto_calibration(get_iface()->get_clock_rate(dboard_iface::UNIT_LMS), 0xf);

+#if 0
    ////////////////////////////////////////////////////////////////////
    // Register RX properties
    ////////////////////////////////////////////////////////////////////
@@ -570,5 +782,6 @@ db_lms6002d::db_lms6002d(ctor_args_t args) : xcvr_dboard_base(args),
    this->get_tx_subtree()->create<uint8_t>("lms6002d/tx_dc_q/value")
        .subscribe(boost::bind(&db_lms6002d::_set_tx_vga1dc_q_int, this, _1))
        .publish(boost::bind(&umtrx_lms6002d_dev::get_tx_vga1dc_q_int, &lms));
+#endif
 }

--- a/host/lib/usrp/umtrx/io_impl.cpp
+++ b/host/lib/usrp/umtrx/io_impl.cpp
@@ -34,10 +34,12 @@
 #include <boost/thread/mutex.hpp>
 #include <boost/make_shared.hpp>
 #include <iostream>
+#include <boost/assign/list_of.hpp>

 using namespace uhd;
 using namespace uhd::usrp;
 using namespace uhd::transport;
+using namespace boost::assign;
 namespace asio = boost::asio;
 namespace pt = boost::posix_time;

@@ -167,37 +169,42 @@ void umtrx_impl::io_init(void) {
    //create new io impl
    _io_impl = UHD_PIMPL_MAKE(io_impl, ());

-    //init first so we dont have an access race
-    BOOST_FOREACH(const std::string &mb, _mbc.keys()){
-        //init the tx xport and flow control monitor
-        _io_impl->tx_xports.push_back(_mbc[mb].tx_dsp_xports[0]);
-        _io_impl->tx_xports.push_back(_mbc[mb].tx_dsp_xports[1]);
-        _io_impl->fc_mons.push_back(flow_control_monitor::sptr(new flow_control_monitor(
-            UMTRX_SRAM_BYTES/_mbc[mb].tx_dsp_xports[0]->get_send_frame_size()
-        )));
-        _io_impl->fc_mons.push_back(flow_control_monitor::sptr(new flow_control_monitor(
-            UMTRX_SRAM_BYTES/_mbc[mb].tx_dsp_xports[1]->get_send_frame_size()
-        )));
+    if (!_notx) {
+        //init first so we dont have an access race
+        BOOST_FOREACH(const std::string &mb, _mbc.keys()){
+            //init the tx xport and flow control monitor
+            _io_impl->tx_xports.push_back(_mbc[mb].tx_dsp_xports[0]);
+            _io_impl->tx_xports.push_back(_mbc[mb].tx_dsp_xports[1]);
+            _io_impl->fc_mons.push_back(flow_control_monitor::sptr(new flow_control_monitor(
+                UMTRX_SRAM_BYTES/_mbc[mb].tx_dsp_xports[0]->get_send_frame_size()
+            )));
+            _io_impl->fc_mons.push_back(flow_control_monitor::sptr(new flow_control_monitor(
+                UMTRX_SRAM_BYTES/_mbc[mb].tx_dsp_xports[1]->get_send_frame_size()
+            )));
+        }
    }

    //allocate streamer weak ptrs containers
    BOOST_FOREACH(const std::string &mb, _mbc.keys()){
        _mbc[mb].rx_streamers.resize(_mbc[mb].rx_dsps.size());
-        _mbc[mb].tx_streamers.resize(_mbc[mb].tx_dsps.size());
+        if (!_notx)
+            _mbc[mb].tx_streamers.resize(_mbc[mb].tx_dsps.size());
    }

-    //create a new pirate thread for each zc if (yarr!!)
-    size_t index = 0;
-    BOOST_FOREACH(const std::string &mb, _mbc.keys()){
-        //spawn a new pirate to plunder the recv booty
-        _io_impl->pirate_tasks.push_back(task::make(boost::bind(
-            &umtrx_impl::io_impl::recv_pirate_loop, _io_impl.get(),
-            _mbc[mb].tx_dsp_xports[0], index++
-        )));
-        _io_impl->pirate_tasks.push_back(task::make(boost::bind(
-            &umtrx_impl::io_impl::recv_pirate_loop, _io_impl.get(),
-            _mbc[mb].tx_dsp_xports[1], index++
-        )));
+    if (!_notx) {
+        //create a new pirate thread for each zc if (yarr!!)
+        size_t index = 0;
+        BOOST_FOREACH(const std::string &mb, _mbc.keys()){
+            //spawn a new pirate to plunder the recv booty
+            _io_impl->pirate_tasks.push_back(task::make(boost::bind(
+                &umtrx_impl::io_impl::recv_pirate_loop, _io_impl.get(),
+                _mbc[mb].tx_dsp_xports[0], index++
+            )));
+            _io_impl->pirate_tasks.push_back(task::make(boost::bind(
+                &umtrx_impl::io_impl::recv_pirate_loop, _io_impl.get(),
+                _mbc[mb].tx_dsp_xports[1], index++
+            )));
+        }
    }
 }

@@ -232,6 +239,9 @@ void umtrx_impl::update_rx_samp_rate(const std::string &mb, const size_t dsp, co
 }

 void umtrx_impl::update_tx_samp_rate(const std::string &mb, const size_t dsp, const double rate){
+    if (_notx)
+        return;
+
    boost::shared_ptr<sph::send_packet_streamer> my_streamer =
        boost::dynamic_pointer_cast<sph::send_packet_streamer>(_mbc[mb].tx_streamers[dsp].lock());
    if (my_streamer.get() == NULL) return;
@@ -248,18 +258,25 @@ void umtrx_impl::update_rates(void){
        BOOST_FOREACH(const std::string &name, _tree->list(root / "rx_dsps")){
            _tree->access<double>(root / "rx_dsps" / name / "rate" / "value").update();
        }
-        BOOST_FOREACH(const std::string &name, _tree->list(root / "tx_dsps")){
-            _tree->access<double>(root / "tx_dsps" / name / "rate" / "value").update();
+        if (!_notx) {
+            BOOST_FOREACH(const std::string &name, _tree->list(root / "tx_dsps")){
+                _tree->access<double>(root / "tx_dsps" / name / "rate" / "value").update();
+            }
        }
    }
 }

+
 void umtrx_impl::update_rx_subdev_spec(const std::string &which_mb, const subdev_spec_t &spec){
    fs_path root = "/mboards/" + which_mb + "/dboards";

    //sanity checking
    validate_subdev_spec(_tree, spec, "rx", which_mb);

+    // Read the current value of the DSP mapping register
+//    boost::uint32_t dsp_mapping = _mbc[which_mb].iface->peek32(U2_REG_SR_ADDR(SR_RX_FRONT_SW));
+    boost::uint32_t dsp_mapping = 0;
+
    //setup DSPs and frontends IQ mux for this spec
    for (size_t i = 0; i < spec.size(); i++){
        const std::string conn = _tree->access<std::string>(root / spec[i].db_name / "rx_frontends" / spec[i].sd_name / "connection").get();
@@ -268,15 +285,14 @@ void umtrx_impl::update_rx_subdev_spec(const std::string &which_mb, const subdev
        // it works in our limited case, so don't bother.
        _mbc[which_mb].rx_dsps[i]->set_mux(conn, fe_swapped);
        _mbc[which_mb].rx_fes[fe_num_for_db(spec[i].db_name)]->set_mux(fe_swapped);
+
+        // Add this subdev spec to the DSP<->FE mapping
+        boost::uint32_t val = (spec[i].db_name == "A")?0:1;
+        dsp_mapping |= (val << i);
    }
+
    //set DSPs to frontends mapping
-    if (spec[0].db_name == "A") {
-        //default: DSP0<-frontend0, DSP1<-frontend1
-        _mbc[which_mb].iface->poke32(U2_REG_SR_ADDR(SR_RX_FRONT_SW), 0);
-    } else {
-        //swapped: DSP0<-frontend1, DSP1<-frontend0
-        _mbc[which_mb].iface->poke32(U2_REG_SR_ADDR(SR_RX_FRONT_SW), 1);
-    }
+    _mbc[which_mb].iface->poke32(U2_REG_SR_ADDR(SR_RX_FRONT_SW), dsp_mapping);

    //compute the new occupancy and resize
    _mbc[which_mb].rx_chan_occ = spec.size();
@@ -285,6 +301,9 @@ void umtrx_impl::update_rx_subdev_spec(const std::string &which_mb, const subdev
 }

 void umtrx_impl::update_tx_subdev_spec(const std::string &which_mb, const subdev_spec_t &spec){
+    if (_notx)
+        return;
+
    fs_path root = "/mboards/" + which_mb + "/dboards";

    //sanity checking
@@ -389,6 +408,9 @@ rx_streamer::sptr umtrx_impl::get_rx_stream(const uhd::stream_args_t &args_){
 * Transmit streamer
 **********************************************************************/
 tx_streamer::sptr umtrx_impl::get_tx_stream(const uhd::stream_args_t &args_){
+    if (_notx)
+        return tx_streamer::sptr();
+
    stream_args_t args = args_;

    //setup defaults for unspecified values
--- a/host/lib/usrp/umtrx/umtrx_impl.cpp
+++ b/host/lib/usrp/umtrx/umtrx_impl.cpp
@@ -44,6 +44,7 @@
 #include <uhd/usrp/dboard_iface.hpp>

 static int verbosity = 0;
+static int version_4xddc = 1;

 using namespace uhd;
 using namespace uhd::usrp;
@@ -106,6 +107,8 @@ static zero_copy_if::sptr make_xport(
 umtrx_impl::umtrx_impl(const device_addr_t &_device_addr)
    : _mcr(26e6/2) // sample rate = ref_clk / 2
 {
+    _notx = version_4xddc ? true : false;
+
    UHD_MSG(status) << "Opening a UmTRX device..." << std::endl;
    device_addr_t device_addr = _device_addr;
    //setup the dsp transport hints (default to a large recv buff)
@@ -204,16 +207,29 @@ umtrx_impl::umtrx_impl(const device_addr_t &_device_addr)
        _mbc[mb].rx_dsp_xports.push_back(make_xport(
            addr, BOOST_STRINGIZE(USRP2_UDP_RX_DSP1_PORT), device_args_i, "recv"
        ));
-        UHD_LOG << "Making transport for TX DSP0..." << std::endl;
-        _mbc[mb].tx_dsp_xports.push_back(make_xport(
-            addr, BOOST_STRINGIZE(USRP2_UDP_TX_DSP0_PORT), device_args_i, "send"
-        ));
-        UHD_LOG << "Making transport for TX DSP1..." << std::endl;
-        _mbc[mb].tx_dsp_xports.push_back(make_xport(
-            addr, BOOST_STRINGIZE(USRP2_UDP_TX_DSP1_PORT), device_args_i, "send"
-        ));
-        //set the filter on the router to take dsp data from these ports
-        _mbc[mb].iface->poke32(U2_REG_ROUTER_CTRL_PORTS, ((uint32_t)USRP2_UDP_TX_DSP1_PORT)<<16 | USRP2_UDP_TX_DSP0_PORT);
+        if (version_4xddc) {
+            UHD_LOG << "Making transport for RX DSP0_2..." << std::endl;
+            _mbc[mb].rx_dsp_xports.push_back(make_xport(
+                addr, BOOST_STRINGIZE(USRP2_UDP_RX_DSP0_2_PORT), device_args_i, "recv"
+            ));
+            UHD_LOG << "Making transport for RX DSP1_2..." << std::endl;
+            _mbc[mb].rx_dsp_xports.push_back(make_xport(
+                addr, BOOST_STRINGIZE(USRP2_UDP_RX_DSP1_2_PORT), device_args_i, "recv"
+            ));
+        }
+
+        if (!_notx) {
+            UHD_LOG << "Making transport for TX DSP0..." << std::endl;
+            _mbc[mb].tx_dsp_xports.push_back(make_xport(
+                                                 addr, BOOST_STRINGIZE(USRP2_UDP_TX_DSP0_PORT), device_args_i, "send"
+                                                 ));
+            UHD_LOG << "Making transport for TX DSP1..." << std::endl;
+            _mbc[mb].tx_dsp_xports.push_back(make_xport(
+                                                 addr, BOOST_STRINGIZE(USRP2_UDP_TX_DSP1_PORT), device_args_i, "send"
+                                                 ));
+            //set the filter on the router to take dsp data from these ports
+            _mbc[mb].iface->poke32(U2_REG_ROUTER_CTRL_PORTS, ((uint32_t)USRP2_UDP_TX_DSP1_PORT)<<16 | USRP2_UDP_TX_DSP0_PORT);
+        }

        ////////////////////////////////////////////////////////////////
        // setup the mboard eeprom
@@ -222,6 +238,9 @@ umtrx_impl::umtrx_impl(const device_addr_t &_device_addr)
            .set(_mbc[mb].iface->mb_eeprom)
            .subscribe(boost::bind(&umtrx_impl::set_mb_eeprom, this, mb, _1));

+        _tree->create<uhd::i2c_iface::sptr>(mb_path / "i2c")
+            .set(static_cast<uhd::i2c_iface::sptr>(_mbc[mb].iface));
+
        ////////////////////////////////////////////////////////////////
        // create clock control objects
        ////////////////////////////////////////////////////////////////
@@ -300,8 +319,12 @@ umtrx_impl::umtrx_impl(const device_addr_t &_device_addr)

        _tree->create<subdev_spec_t>(mb_path / "rx_subdev_spec")
            .subscribe(boost::bind(&umtrx_impl::update_rx_subdev_spec, this, mb, _1));
-        _tree->create<subdev_spec_t>(mb_path / "tx_subdev_spec")
-            .subscribe(boost::bind(&umtrx_impl::update_tx_subdev_spec, this, mb, _1));
+        if (!_notx) {
+            _tree->create<subdev_spec_t>(mb_path / "tx_subdev_spec")
+                    .subscribe(boost::bind(&umtrx_impl::update_tx_subdev_spec, this, mb, _1));
+        } else {
+            _tree->create<subdev_spec_t>(mb_path / "tx_subdev_spec"); // otherwise rx_multi_samples crashes
+        }

        BOOST_FOREACH(const std::string &db, _mbc[mb].dbc.keys()){
            const fs_path rx_fe_path = mb_path / "rx_frontends" / db;
@@ -318,12 +341,15 @@ umtrx_impl::umtrx_impl(const device_addr_t &_device_addr)
            _tree->create<std::complex<double> >(rx_fe_path / "iq_balance" / "value")
                .subscribe(boost::bind(&rx_frontend_core_200::set_iq_balance, rx_fe, _1))
                .set(std::polar<double>(1.0, 0.0));
-            _tree->create<std::complex<double> >(tx_fe_path / "dc_offset" / "value")
-                .coerce(boost::bind(&tx_frontend_core_200::set_dc_offset, tx_fe, _1))
-                .set(std::complex<double>(0.0, 0.0));
-            _tree->create<std::complex<double> >(tx_fe_path / "iq_balance" / "value")
-                .subscribe(boost::bind(&tx_frontend_core_200::set_iq_balance, tx_fe, _1))
-                .set(std::polar<double>(1.0, 0.0));
+
+            if (!_notx) {
+                _tree->create<std::complex<double> >(tx_fe_path / "dc_offset" / "value")
+                        .coerce(boost::bind(&tx_frontend_core_200::set_dc_offset, tx_fe, _1))
+                        .set(std::complex<double>(0.0, 0.0));
+                _tree->create<std::complex<double> >(tx_fe_path / "iq_balance" / "value")
+                        .subscribe(boost::bind(&tx_frontend_core_200::set_iq_balance, tx_fe, _1))
+                        .set(std::polar<double>(1.0, 0.0));
+            }
        }

        ////////////////////////////////////////////////////////////////
@@ -335,6 +361,14 @@ umtrx_impl::umtrx_impl(const device_addr_t &_device_addr)
        _mbc[mb].rx_dsps.push_back(rx_dsp_core_200::make(
            _mbc[mb].iface, U2_REG_SR_ADDR(SR_RX_DSP1), U2_REG_SR_ADDR(SR_RX_CTRL1), USRP2_RX_SID_BASE + 1, true
        ));
+        if (version_4xddc) {
+            _mbc[mb].rx_dsps.push_back(rx_dsp_core_200::make(
+                _mbc[mb].iface, U2_REG_SR_ADDR(SR_RX_DSP0_2), U2_REG_SR_ADDR(SR_RX_CTRL0_2), USRP2_RX_SID_BASE + 2, true
+            ));
+            _mbc[mb].rx_dsps.push_back(rx_dsp_core_200::make(
+                _mbc[mb].iface, U2_REG_SR_ADDR(SR_RX_DSP1_2), U2_REG_SR_ADDR(SR_RX_CTRL1_2), USRP2_RX_SID_BASE + 3, true
+            ));
+        }
        for (size_t dspno = 0; dspno < _mbc[mb].rx_dsps.size(); dspno++){
            _mbc[mb].rx_dsps[dspno]->set_link_rate(USRP2_LINK_RATE_BPS);
            _tree->access<double>(mb_path / "tick_rate")
@@ -357,42 +391,45 @@ umtrx_impl::umtrx_impl(const device_addr_t &_device_addr)
        ////////////////////////////////////////////////////////////////
        // create tx dsp control objects
        ////////////////////////////////////////////////////////////////
-        _mbc[mb].tx_dsps.push_back(tx_dsp_core_200::make(
-            _mbc[mb].iface, U2_REG_SR_ADDR(SR_TX_DSP0), U2_REG_SR_ADDR(SR_TX_CTRL0), USRP2_TX_ASYNC_SID_BASE+0
-        ));
-        _mbc[mb].tx_dsps.push_back(tx_dsp_core_200::make(
-            _mbc[mb].iface, U2_REG_SR_ADDR(SR_TX_DSP1), U2_REG_SR_ADDR(SR_TX_CTRL1), USRP2_TX_ASYNC_SID_BASE+1
-        ));
-        for (size_t dspno = 0; dspno < _mbc[mb].tx_dsps.size(); dspno++){
-            _mbc[mb].tx_dsps[dspno]->set_link_rate(USRP2_LINK_RATE_BPS);
-            _tree->access<double>(mb_path / "tick_rate")
-                .subscribe(boost::bind(&tx_dsp_core_200::set_tick_rate, _mbc[mb].tx_dsps[dspno], _1));
-            fs_path tx_dsp_path = mb_path / str(boost::format("tx_dsps/%u") % dspno);
-            _tree->create<meta_range_t>(tx_dsp_path / "rate/range")
-                .publish(boost::bind(&tx_dsp_core_200::get_host_rates, _mbc[mb].tx_dsps[dspno]));
-            _tree->create<double>(tx_dsp_path / "rate/value")
-                .set(_mcr/12) //some default
-                .coerce(boost::bind(&tx_dsp_core_200::set_host_rate, _mbc[mb].tx_dsps[dspno], _1))
-                .subscribe(boost::bind(&umtrx_impl::update_tx_samp_rate, this, mb, dspno, _1));
-            _tree->create<double>(tx_dsp_path / "freq/value")
-                .coerce(boost::bind(&tx_dsp_core_200::set_freq, _mbc[mb].tx_dsps[dspno], _1));
-            _tree->create<meta_range_t>(tx_dsp_path / "freq/range")
-                .publish(boost::bind(&tx_dsp_core_200::get_freq_range, _mbc[mb].tx_dsps[dspno]));
+        if (!_notx) {
+            _mbc[mb].tx_dsps.push_back(tx_dsp_core_200::make(
+                                           _mbc[mb].iface, U2_REG_SR_ADDR(SR_TX_DSP0), U2_REG_SR_ADDR(SR_TX_CTRL0), USRP2_TX_ASYNC_SID_BASE+0
+                                           ));
+            _mbc[mb].tx_dsps.push_back(tx_dsp_core_200::make(
+                                           _mbc[mb].iface, U2_REG_SR_ADDR(SR_TX_DSP1), U2_REG_SR_ADDR(SR_TX_CTRL1), USRP2_TX_ASYNC_SID_BASE+1
+                                           ));
+            for (size_t dspno = 0; dspno < _mbc[mb].tx_dsps.size(); dspno++){
+                _mbc[mb].tx_dsps[dspno]->set_link_rate(USRP2_LINK_RATE_BPS);
+                _tree->access<double>(mb_path / "tick_rate")
+                        .subscribe(boost::bind(&tx_dsp_core_200::set_tick_rate, _mbc[mb].tx_dsps[dspno], _1));
+                fs_path tx_dsp_path = mb_path / str(boost::format("tx_dsps/%u") % dspno);
+                _tree->create<meta_range_t>(tx_dsp_path / "rate/range")
+                        .publish(boost::bind(&tx_dsp_core_200::get_host_rates, _mbc[mb].tx_dsps[dspno]));
+                _tree->create<double>(tx_dsp_path / "rate/value")
+                        .set(_mcr/12) //some default
+                        .coerce(boost::bind(&tx_dsp_core_200::set_host_rate, _mbc[mb].tx_dsps[dspno], _1))
+                        .subscribe(boost::bind(&umtrx_impl::update_tx_samp_rate, this, mb, dspno, _1));
+                _tree->create<double>(tx_dsp_path / "freq/value")
+                        .coerce(boost::bind(&tx_dsp_core_200::set_freq, _mbc[mb].tx_dsps[dspno], _1));
+                _tree->create<meta_range_t>(tx_dsp_path / "freq/range")
+                        .publish(boost::bind(&tx_dsp_core_200::get_freq_range, _mbc[mb].tx_dsps[dspno]));
+            }
+
+            //setup dsp flow control
+            const double ups_per_sec = device_args_i.cast<double>("ups_per_sec", 20);
+            const size_t send_frame_size = _mbc[mb].tx_dsp_xports[0]->get_send_frame_size();
+            const double ups_per_fifo = device_args_i.cast<double>("ups_per_fifo", 8.0);
+            _mbc[mb].tx_dsps[0]->set_updates(
+                        (ups_per_sec > 0.0)? size_t(get_master_clock_rate()/*approx tick rate*//ups_per_sec) : 0,
+                        (ups_per_fifo > 0.0)? size_t(UMTRX_SRAM_BYTES/ups_per_fifo/send_frame_size) : 0
+                                              );
+            _mbc[mb].tx_dsps[1]->set_updates(
+                        (ups_per_sec > 0.0)? size_t(get_master_clock_rate()/*approx tick rate*//ups_per_sec) : 0,
+                        (ups_per_fifo > 0.0)? size_t(UMTRX_SRAM_BYTES/ups_per_fifo/send_frame_size) : 0
+                                              );
+        } else {
+            _tree->create<int>(mb_path / "tx_dsps"); // Dummy node to work uhd_usrp_probe
        }
-
-        //setup dsp flow control
-        const double ups_per_sec = device_args_i.cast<double>("ups_per_sec", 20);
-        const size_t send_frame_size = _mbc[mb].tx_dsp_xports[0]->get_send_frame_size();
-        const double ups_per_fifo = device_args_i.cast<double>("ups_per_fifo", 8.0);
-        _mbc[mb].tx_dsps[0]->set_updates(
-            (ups_per_sec > 0.0)? size_t(get_master_clock_rate()/*approx tick rate*//ups_per_sec) : 0,
-            (ups_per_fifo > 0.0)? size_t(UMTRX_SRAM_BYTES/ups_per_fifo/send_frame_size) : 0
-        );
-        _mbc[mb].tx_dsps[1]->set_updates(
-            (ups_per_sec > 0.0)? size_t(get_master_clock_rate()/*approx tick rate*//ups_per_sec) : 0,
-            (ups_per_fifo > 0.0)? size_t(UMTRX_SRAM_BYTES/ups_per_fifo/send_frame_size) : 0
-        );
-
        ////////////////////////////////////////////////////////////////
        // create time control objects
        ////////////////////////////////////////////////////////////////
@@ -430,10 +467,15 @@ umtrx_impl::umtrx_impl(const device_addr_t &_device_addr)

        // LMS dboard do not have physical eeprom so we just hardcode values from host/lib/usrp/dboard/db_lms.cpp
        dboard_eeprom_t rx_db_eeprom, tx_db_eeprom, gdb_eeprom;
-        rx_db_eeprom.id = 0xfa07;
        rx_db_eeprom.revision = _mbc[mb].iface->mb_eeprom["revision"];
-        tx_db_eeprom.id = 0xfa09;
        tx_db_eeprom.revision = _mbc[mb].iface->mb_eeprom["revision"];
+        if (version_4xddc) {
+            rx_db_eeprom.id = 0xfa0a;
+            tx_db_eeprom.id = 0xfa0b;
+        } else {
+            rx_db_eeprom.id = 0xfa07;
+            tx_db_eeprom.id = 0xfa09;
+        }
        //gdb_eeprom.id = 0x0000;

        BOOST_FOREACH(const std::string &board, _mbc[mb].dbc.keys()){
@@ -459,33 +501,37 @@ umtrx_impl::umtrx_impl(const device_addr_t &_device_addr)

            _tree->create<dboard_eeprom_t>(mb_path / "dboards" / board / "gdb_eeprom")
                .set(gdb_eeprom);
-            
+
            _tree->create<dboard_iface::sptr>(mb_path / "dboards" / board / "iface").set(_mbc[mb].dbc[board].dboard_iface);

-            //bind frontend corrections to the dboard freq props
-            const fs_path db_tx_fe_path = mb_path / "dboards" / board / "tx_frontends";
-            BOOST_FOREACH(const std::string &name, _tree->list(db_tx_fe_path)){
-                _tree->access<double>(db_tx_fe_path / name / "freq" / "value")
-                    .subscribe(boost::bind(&umtrx_impl::set_tx_fe_corrections, this, mb, board, _1));
+            if (!_notx) {
+                //bind frontend corrections to the dboard freq props
+                const fs_path db_tx_fe_path = mb_path / "dboards" / board / "tx_frontends";
+                BOOST_FOREACH(const std::string &name, _tree->list(db_tx_fe_path)){
+                    _tree->access<double>(db_tx_fe_path / name / "freq" / "value")
+                            .subscribe(boost::bind(&umtrx_impl::set_tx_fe_corrections, this, mb, board, _1));
+                }
            }
            const fs_path db_rx_fe_path = mb_path / "dboards" / board / "rx_frontends";
            BOOST_FOREACH(const std::string &name, _tree->list(db_rx_fe_path)){
                _tree->access<double>(db_rx_fe_path / name / "freq" / "value")
-                    .subscribe(boost::bind(&umtrx_impl::set_rx_fe_corrections, this, mb, board, _1));
+                        .subscribe(boost::bind(&umtrx_impl::set_rx_fe_corrections, this, mb, board, _1));
            }
-
-            //set Tx DC calibration values, which are read from mboard EEPROM
-            std::string tx_name = (board=="A")?"tx1":"tx2";
-            if (_mbc[mb].iface->mb_eeprom.has_key(tx_name+"-vga1-dc-i") and not _mbc[mb].iface->mb_eeprom[tx_name+"-vga1-dc-i"].empty()) {
-                BOOST_FOREACH(const std::string &name, _tree->list(db_tx_fe_path)){
-                    _tree->access<uint8_t>(db_tx_fe_path / name / "lms6002d/tx_dc_i/value")
-                        .set(boost::lexical_cast<int>(_mbc[mb].iface->mb_eeprom[tx_name+"-vga1-dc-i"]));
+            if (!_notx) {
+                const fs_path db_tx_fe_path = mb_path / "dboards" / board / "tx_frontends";
+                //set Tx DC calibration values, which are read from mboard EEPROM
+                std::string tx_name = (board=="A")?"tx1":"tx2";
+                if (_mbc[mb].iface->mb_eeprom.has_key(tx_name+"-vga1-dc-i") and not _mbc[mb].iface->mb_eeprom[tx_name+"-vga1-dc-i"].empty()) {
+                    BOOST_FOREACH(const std::string &name, _tree->list(db_tx_fe_path)){
+                        _tree->access<uint8_t>(db_tx_fe_path / name / "lms6002d/tx_dc_i/value")
+                                .set(boost::lexical_cast<int>(_mbc[mb].iface->mb_eeprom[tx_name+"-vga1-dc-i"]));
+                    }
                }
-            }
-            if (_mbc[mb].iface->mb_eeprom.has_key(tx_name+"-vga1-dc-q") and not _mbc[mb].iface->mb_eeprom[tx_name+"-vga1-dc-q"].empty()) {
-                BOOST_FOREACH(const std::string &name, _tree->list(db_tx_fe_path)){
-                    _tree->access<uint8_t>(db_tx_fe_path / name / "lms6002d/tx_dc_q/value")
-                        .set(boost::lexical_cast<int>(_mbc[mb].iface->mb_eeprom[tx_name+"-vga1-dc-q"]));
+                if (_mbc[mb].iface->mb_eeprom.has_key(tx_name+"-vga1-dc-q") and not _mbc[mb].iface->mb_eeprom[tx_name+"-vga1-dc-q"].empty()) {
+                    BOOST_FOREACH(const std::string &name, _tree->list(db_tx_fe_path)){
+                        _tree->access<uint8_t>(db_tx_fe_path / name / "lms6002d/tx_dc_q/value")
+                                .set(boost::lexical_cast<int>(_mbc[mb].iface->mb_eeprom[tx_name+"-vga1-dc-q"]));
+                    }
                }
            }
        }
@@ -507,7 +553,12 @@ umtrx_impl::umtrx_impl(const device_addr_t &_device_addr)
        fs_path root = "/mboards/" + mb;

        _tree->access<subdev_spec_t>(root / "rx_subdev_spec").set(subdev_spec_t("A:" + _tree->list(root / "dboards/A/rx_frontends").at(0)));
-        _tree->access<subdev_spec_t>(root / "tx_subdev_spec").set(subdev_spec_t("A:" + _tree->list(root / "dboards/A/tx_frontends").at(0)));
+
+        if (!_notx)
+            _tree->access<subdev_spec_t>(root / "tx_subdev_spec").set(subdev_spec_t("A:" + _tree->list(root / "dboards/A/tx_frontends").at(0)));
+        else
+            _tree->access<subdev_spec_t>(root / "tx_subdev_spec").set(subdev_spec_t(""));
+
        _tree->access<std::string>(root / "clock_source/value").set("internal");
        _tree->access<std::string>(root / "time_source/value").set("none");

@@ -523,10 +574,12 @@ umtrx_impl::umtrx_impl(const device_addr_t &_device_addr)
 }

 umtrx_impl::~umtrx_impl(void){UHD_SAFE_CALL(
+                if (!_notx) {
    BOOST_FOREACH(const std::string &mb, _mbc.keys()){
        _mbc[mb].tx_dsps[0]->set_updates(0, 0);
        _mbc[mb].tx_dsps[1]->set_updates(0, 0);
    }
+                }
 )}

 void umtrx_impl::set_mb_eeprom(const std::string &mb, const uhd::usrp::mboard_eeprom_t &mb_eeprom){
@@ -538,7 +591,8 @@ void umtrx_impl::set_rx_fe_corrections(const std::string &mb, const std::string
 }

 void umtrx_impl::set_tx_fe_corrections(const std::string &mb, const std::string &board, const double lo_freq){
-    apply_tx_fe_corrections(this->get_tree()->subtree("/mboards/" + mb), board, lo_freq);
+    if (!_notx)
+        apply_tx_fe_corrections(this->get_tree()->subtree("/mboards/" + mb), board, lo_freq);
 }

 void umtrx_impl::set_tcxo_dac(const std::string &mb, const uint16_t val){
--- a/host/lib/usrp/umtrx/umtrx_impl.hpp
+++ b/host/lib/usrp/umtrx/umtrx_impl.hpp
@@ -80,6 +80,7 @@ public:
    bool recv_async_msg(uhd::async_metadata_t &, double);

 private:
+    bool _notx; /**< Disable TX DSPs */
    uhd::property_tree::sptr _tree;
    struct mb_container_type{
        usrp2_iface::sptr iface;
--- a/host/lib/usrp/umtrx/umtrx_regs.hpp
+++ b/host/lib/usrp/umtrx/umtrx_regs.hpp
@@ -45,17 +45,21 @@
 #define SR_RX_FRONT0  20   // 5
 #define SR_RX_FRONT1  25   // 5

-#define SR_RX_CTRL0  32   // 9
-#define SR_RX_DSP0   48   // 7
-#define SR_RX_CTRL1  80   // 9
-#define SR_RX_DSP1   96   // 7
+#define SR_RX_CTRL0  32   // 10
+#define SR_RX_DSP0   42   // 7
+#define SR_RX_CTRL1  49   // 10
+#define SR_RX_DSP1   59   // 7
+#define SR_RX_CTRL0_2  66   // 10
+#define SR_RX_DSP0_2   76   // 7
+#define SR_RX_CTRL1_2  117   // 10
+#define SR_RX_DSP1_2   127   // 7

-#define SR_TX_FRONT0 110   // ?
-#define SR_TX_CTRL0  126   // 6
-#define SR_TX_DSP0   135   // 5
-#define SR_TX_FRONT1 145   // ?
-#define SR_TX_CTRL1  161   // 6
-#define SR_TX_DSP1   170   // 5
+#define SR_TX_FRONT0 150   // ?
+#define SR_TX_CTRL0  150   // 6
+#define SR_TX_DSP0   150   // 5
+#define SR_TX_FRONT1 150   // ?
+#define SR_TX_CTRL1  150   // 6
+#define SR_TX_DSP1   150   // 5

 // DSPs to frontends mapping controls
 #define SR_RX_FRONT_SW 176 // 1
--- a/host/lib/usrp/usrp2/fw_common.h
+++ b/host/lib/usrp/usrp2/fw_common.h
@@ -42,8 +42,10 @@ extern "C" {
 #define USRP2_UDP_CTRL_PORT 49152
 //#define USRP2_UDP_UPDATE_PORT 49154
 #define USRP2_UDP_RX_DSP0_PORT 49156
+#define USRP2_UDP_RX_DSP0_2_PORT 49157
 #define USRP2_UDP_TX_DSP0_PORT 49157
 #define USRP2_UDP_RX_DSP1_PORT 49158
+#define USRP2_UDP_RX_DSP1_2_PORT 49159
 #define USRP2_UDP_TX_DSP1_PORT 49159
 #define USRP2_UDP_UART_BASE_PORT 49170
 #define USRP2_UDP_UART_GPS_PORT 49172
--- a/host/utils/usrp_burn_mb_eeprom.cpp
+++ b/host/utils/usrp_burn_mb_eeprom.cpp
@@ -23,10 +23,14 @@
 #include <boost/format.hpp>
 #include <iostream>

+#include <uhd/types/serial.hpp>
+
 namespace po = boost::program_options;
+static const boost::uint8_t N100_EEPROM_ADDR = 0x50;

 int UHD_SAFE_MAIN(int argc, char *argv[]){
    std::string args, key, val;
+    unsigned dump_sz, off_sz;

    po::options_description desc("Allowed options");
    desc.add_options()
@@ -34,6 +38,10 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){
        ("args", po::value<std::string>(&args)->default_value(""), "device address args [default = \"\"]")
        ("key", po::value<std::string>(&key), "the indentifier for a value in EEPROM")
        ("val", po::value<std::string>(&val), "the new value to set, omit for readback")
+        ("sz", po::value<unsigned>(&dump_sz)->default_value(256), "size of dump or erase")
+        ("off", po::value<unsigned>(&off_sz)->default_value(0), "size of dump or erase")
+        ("dump", "Dump EEPROM memory")
+        ("erase", "Erase EEPROM memory")
    ;

    po::variables_map vm;
@@ -41,7 +49,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){
    po::notify(vm);

    //print the help message
-    if (vm.count("help") or not vm.count("key")){
+    if (vm.count("help") or not (vm.count("key") or vm.count("dump") or vm.count("erase"))){
        std::cout << boost::format("USRP Burn Motherboard EEPROM %s") % desc << std::endl;
        std::cout << boost::format(
            "Omit the value argument to perform a readback,\n"
@@ -55,7 +63,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){
    uhd::property_tree::sptr tree = dev->get_tree();
    std::cout << std::endl;

-    if (true /*always readback*/){
+    if (vm.count("key")) {
        std::cout << "Fetching current settings from EEPROM..." << std::endl;
        uhd::usrp::mboard_eeprom_t mb_eeprom = tree->access<uhd::usrp::mboard_eeprom_t>("/mboards/0/eeprom").get();
        if (not mb_eeprom.has_key(key)){
@@ -72,6 +80,42 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){
        std::cout << "Power-cycle the USRP device for the changes to take effect." << std::endl;
        std::cout << std::endl;
    }
+    if (vm.count("dump")) {
+        uhd::i2c_iface::sptr i2c;
+        i2c = tree->access<uhd::i2c_iface::sptr>("/mboards/0/i2c").get();
+        unsigned part_off = off_sz;
+        unsigned part_sz = dump_sz;
+        do {
+            unsigned read_sz = (part_sz > 20) ? 20 : part_sz;
+
+            uhd::byte_vector_t v = i2c->read_eeprom(N100_EEPROM_ADDR, part_off, read_sz);
+            unsigned i;
+            for (i = 0; i < v.size(); i++) {
+                fprintf(stderr, "%d: %02x '%c'\n", part_off + i, v[i], (v[i] > 31 ? v[i] : '?'));
+            }
+
+            part_sz -= read_sz;
+            part_off += read_sz;
+        } while (part_sz > 0);
+    }
+    if (vm.count("erase")) {
+        uhd::i2c_iface::sptr i2c;
+        i2c = tree->access<uhd::i2c_iface::sptr>("/mboards/0/i2c").get();
+        unsigned part_off = off_sz;
+        unsigned part_sz = dump_sz;
+        do {
+            unsigned read_sz = (part_sz > 20) ? 20 : part_sz;
+
+            uhd::byte_vector_t vec(read_sz);
+            std::fill(vec.begin(), vec.end(), 0xFF);
+
+            i2c->write_eeprom(N100_EEPROM_ADDR, part_off, vec);
+            //uhd::byte_vector_t v = i2c->read_eeprom(N100_EEPROM_ADDR, part_off, read_sz);
+
+            part_sz -= read_sz;
+            part_off += read_sz;
+        } while (part_sz > 0);
+    }

    std::cout << "Done" << std::endl;
    return 0;
Author	SHA1	Message	Date
Sergey Kostanbaev	a8402d9c58	Add --dump & --erase options for EEPROM	2014-10-27 11:47:38 -04:00
Sergey Kostanbaev	d1ca71adb9	Fix 4DDC version	2014-10-27 11:47:16 -04:00
Alexander Chemeris	bc0932006b	Host: Support multiple DSPs connection to a single LMS. We introduce a master LMS class and a wrapper to handle access to LMS from multiple DSPs.	2013-08-22 19:37:26 +04:00
Alexander Chemeris	8c75496c57	Host: Better debug output for db_lms.cpp	2013-08-22 19:37:26 +04:00
Andrew Karpenkov	5d691ee088	FPGA: Frontend switch was changed according with 4ddc mode.	2013-08-22 19:37:25 +04:00
Alexander Chemeris	10a88d791a	HOST: Remove Tx DSPs, add two Rx DSPs.	2013-08-22 19:37:25 +04:00
Andrew Karpenkov	7ef81ee734	ZPU: Remove Tx DSPs, add two Rx DSPs.	2013-08-22 19:37:25 +04:00
Andrew Karpenkov	3eb489d89f	FPGA: Remove Tx DSPs, add two Rx DSPs.	2013-08-22 19:37:25 +04:00