mirror of
https://github.com/fairwaves/UHD-Fairwaves.git
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313 lines
16 KiB
Verilog
313 lines
16 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// Boot RAM for S3A, 8KB, dual port
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// RAMB16BWE_S36_S36: 512 x 32 + 4 Parity bits byte-wide write Dual-Port RAM
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// Spartan-3A Xilinx HDL Libraries Guide, version 10.1.1
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module bootram
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(input clk, input reset,
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input [13:0] if_adr,
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output [31:0] if_data,
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input [13:0] dwb_adr_i,
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input [31:0] dwb_dat_i,
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output [31:0] dwb_dat_o,
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input dwb_we_i,
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output reg dwb_ack_o,
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input dwb_stb_i,
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input [3:0] dwb_sel_i);
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wire [31:0] DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7;
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wire [31:0] DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7;
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wire ENB0, ENB1, ENB2, ENB3, ENB4, ENB5, ENB6, ENB7;
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wire [3:0] WEB;
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reg [2:0] delayed_if_bank;
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always @(posedge clk)
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delayed_if_bank <= if_adr[13:11];
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assign if_data = delayed_if_bank[2] ?
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(delayed_if_bank[1] ? (delayed_if_bank[0] ? DOA7 : DOA6) : (delayed_if_bank[0] ? DOA5 : DOA4))
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: (delayed_if_bank[1] ? (delayed_if_bank[0] ? DOA3 : DOA2) : (delayed_if_bank[0] ? DOA1 : DOA0));
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assign dwb_dat_o = dwb_adr_i[13] ?
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(dwb_adr_i[12] ? (dwb_adr_i[11] ? DOB7 : DOB6) : (dwb_adr_i[11] ? DOB5 : DOB4))
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: (dwb_adr_i[12] ? (dwb_adr_i[11] ? DOB3 : DOB2) : (dwb_adr_i[11] ? DOB1 : DOB0));
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always @(posedge clk)
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if(reset)
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dwb_ack_o <= 0;
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else
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dwb_ack_o <= dwb_stb_i & ~dwb_ack_o;
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assign ENB0 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b000);
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assign ENB1 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b001);
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assign ENB2 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b010);
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assign ENB3 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b011);
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assign ENB4 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b100);
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assign ENB5 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b101);
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assign ENB6 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b110);
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assign ENB7 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b111);
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assign WEB = {4{dwb_we_i}} & dwb_sel_i;
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RAMB16BWE_S36_S36
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#(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
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.INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
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.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
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.SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
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.SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
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.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
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.WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE
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RAM0
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(.DOA(DOA0), // Port A 32-bit Data Output
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.DOPA(), // Port A 4-bit Parity Output
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.ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
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.CLKA(clk), // Port A 1-bit Clock
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.DIA(32'hffffffff), // Port A 32-bit Data Input
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.DIPA(4'hf), // Port A 4-bit parity Input
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.ENA(1'b1), // Port A 1-bit RAM Enable Input
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.SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input
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.WEA(1'b0), // Port A 4-bit Write Enable Input
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.DOB(DOB0), // Port B 32-bit Data Output
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.DOPB(), // Port B 4-bit Parity Output
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.ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
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.CLKB(clk), // Port B 1-bit Clock
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.DIB(dwb_dat_i), // Port B 32-bit Data Input
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.DIPB(4'hf), // Port-B 4-bit parity Input
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.ENB(ENB0), // Port B 1-bit RAM Enable Input
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.SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input
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.WEB(WEB) // Port B 4-bit Write Enable Input
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); // End of RAMB16BWE_S36_S36_inst instantiation
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RAMB16BWE_S36_S36
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#(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
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.INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
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.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
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.SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
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.SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
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.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
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.WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE
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RAM1
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(.DOA(DOA1), // Port A 32-bit Data Output
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.DOPA(), // Port A 4-bit Parity Output
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.ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
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.CLKA(clk), // Port A 1-bit Clock
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.DIA(32'hffffffff), // Port A 32-bit Data Input
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.DIPA(4'hf), // Port A 4-bit parity Input
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.ENA(1'b1), // Port A 1-bit RAM Enable Input
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.SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input
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.WEA(1'b0), // Port A 4-bit Write Enable Input
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.DOB(DOB1), // Port B 32-bit Data Output
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.DOPB(), // Port B 4-bit Parity Output
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.ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
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.CLKB(clk), // Port B 1-bit Clock
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.DIB(dwb_dat_i), // Port B 32-bit Data Input
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.DIPB(4'hf), // Port-B 4-bit parity Input
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.ENB(ENB1), // Port B 1-bit RAM Enable Input
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.SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input
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.WEB(WEB) // Port B 4-bit Write Enable Input
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); // End of RAMB16BWE_S36_S36_inst instantiation
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RAMB16BWE_S36_S36
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#(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
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.INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
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.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
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.SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
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.SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
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.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
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.WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE
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RAM2
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(.DOA(DOA2), // Port A 32-bit Data Output
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.DOPA(), // Port A 4-bit Parity Output
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.ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
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.CLKA(clk), // Port A 1-bit Clock
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.DIA(32'hffffffff), // Port A 32-bit Data Input
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.DIPA(4'hf), // Port A 4-bit parity Input
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.ENA(1'b1), // Port A 1-bit RAM Enable Input
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.SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input
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.WEA(1'b0), // Port A 4-bit Write Enable Input
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.DOB(DOB2), // Port B 32-bit Data Output
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.DOPB(), // Port B 4-bit Parity Output
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.ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
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.CLKB(clk), // Port B 1-bit Clock
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.DIB(dwb_dat_i), // Port B 32-bit Data Input
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.DIPB(4'hf), // Port-B 4-bit parity Input
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.ENB(ENB2), // Port B 1-bit RAM Enable Input
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.SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input
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.WEB(WEB) // Port B 4-bit Write Enable Input
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); // End of RAMB16BWE_S36_S36_inst instantiation
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RAMB16BWE_S36_S36
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#(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
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.INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
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.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
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.SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
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.SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
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.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
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.WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE
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RAM3
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(.DOA(DOA3), // Port A 32-bit Data Output
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.DOPA(), // Port A 4-bit Parity Output
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.ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
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.CLKA(clk), // Port A 1-bit Clock
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.DIA(32'hffffffff), // Port A 32-bit Data Input
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.DIPA(4'hf), // Port A 4-bit parity Input
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.ENA(1'b1), // Port A 1-bit RAM Enable Input
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.SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input
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.WEA(1'b0), // Port A 4-bit Write Enable Input
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.DOB(DOB3), // Port B 32-bit Data Output
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.DOPB(), // Port B 4-bit Parity Output
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.ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
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.CLKB(clk), // Port B 1-bit Clock
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.DIB(dwb_dat_i), // Port B 32-bit Data Input
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.DIPB(4'hf), // Port-B 4-bit parity Input
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.ENB(ENB3), // Port B 1-bit RAM Enable Input
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.SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input
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.WEB(WEB) // Port B 4-bit Write Enable Input
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); // End of RAMB16BWE_S36_S36_inst instantiation
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RAMB16BWE_S36_S36
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#(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
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.INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
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.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
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.SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
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.SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
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.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
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.WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE
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RAM4
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(.DOA(DOA4), // Port A 32-bit Data Output
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.DOPA(), // Port A 4-bit Parity Output
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.ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
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.CLKA(clk), // Port A 1-bit Clock
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.DIA(32'hffffffff), // Port A 32-bit Data Input
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.DIPA(4'hf), // Port A 4-bit parity Input
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.ENA(1'b1), // Port A 1-bit RAM Enable Input
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.SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input
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.WEA(1'b0), // Port A 4-bit Write Enable Input
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.DOB(DOB4), // Port B 32-bit Data Output
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.DOPB(), // Port B 4-bit Parity Output
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.ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
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.CLKB(clk), // Port B 1-bit Clock
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.DIB(dwb_dat_i), // Port B 32-bit Data Input
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.DIPB(4'hf), // Port-B 4-bit parity Input
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.ENB(ENB4), // Port B 1-bit RAM Enable Input
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.SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input
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.WEB(WEB) // Port B 4-bit Write Enable Input
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); // End of RAMB16BWE_S36_S36_inst instantiation
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RAMB16BWE_S36_S36
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#(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
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.INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
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.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
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.SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
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.SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
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.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
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.WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE
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RAM5
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(.DOA(DOA5), // Port A 32-bit Data Output
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.DOPA(), // Port A 4-bit Parity Output
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.ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
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.CLKA(clk), // Port A 1-bit Clock
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.DIA(32'hffffffff), // Port A 32-bit Data Input
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.DIPA(4'hf), // Port A 4-bit parity Input
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.ENA(1'b1), // Port A 1-bit RAM Enable Input
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.SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input
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.WEA(1'b0), // Port A 4-bit Write Enable Input
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.DOB(DOB5), // Port B 32-bit Data Output
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.DOPB(), // Port B 4-bit Parity Output
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.ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
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.CLKB(clk), // Port B 1-bit Clock
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.DIB(dwb_dat_i), // Port B 32-bit Data Input
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.DIPB(4'hf), // Port-B 4-bit parity Input
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.ENB(ENB5), // Port B 1-bit RAM Enable Input
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.SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input
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.WEB(WEB) // Port B 4-bit Write Enable Input
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); // End of RAMB16BWE_S36_S36_inst instantiation
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RAMB16BWE_S36_S36
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#(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
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.INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
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.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
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.SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
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.SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
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.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
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.WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE
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RAM6
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(.DOA(DOA6), // Port A 32-bit Data Output
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.DOPA(), // Port A 4-bit Parity Output
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.ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
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.CLKA(clk), // Port A 1-bit Clock
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.DIA(32'hffffffff), // Port A 32-bit Data Input
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.DIPA(4'hf), // Port A 4-bit parity Input
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.ENA(1'b1), // Port A 1-bit RAM Enable Input
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.SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input
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.WEA(1'b0), // Port A 4-bit Write Enable Input
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.DOB(DOB6), // Port B 32-bit Data Output
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.DOPB(), // Port B 4-bit Parity Output
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.ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
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.CLKB(clk), // Port B 1-bit Clock
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.DIB(dwb_dat_i), // Port B 32-bit Data Input
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.DIPB(4'hf), // Port-B 4-bit parity Input
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.ENB(ENB6), // Port B 1-bit RAM Enable Input
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.SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input
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.WEB(WEB) // Port B 4-bit Write Enable Input
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); // End of RAMB16BWE_S36_S36_inst instantiation
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RAMB16BWE_S36_S36
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#(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
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.INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
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.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
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.SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
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.SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
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.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
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.WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE
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RAM7
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(.DOA(DOA7), // Port A 32-bit Data Output
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.DOPA(), // Port A 4-bit Parity Output
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.ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
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.CLKA(clk), // Port A 1-bit Clock
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.DIA(32'hffffffff), // Port A 32-bit Data Input
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.DIPA(4'hf), // Port A 4-bit parity Input
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.ENA(1'b1), // Port A 1-bit RAM Enable Input
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.SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input
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.WEA(1'b0), // Port A 4-bit Write Enable Input
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.DOB(DOB7), // Port B 32-bit Data Output
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.DOPB(), // Port B 4-bit Parity Output
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.ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
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.CLKB(clk), // Port B 1-bit Clock
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.DIB(dwb_dat_i), // Port B 32-bit Data Input
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.DIPB(4'hf), // Port-B 4-bit parity Input
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.ENB(ENB7), // Port B 1-bit RAM Enable Input
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.SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input
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.WEB(WEB) // Port B 4-bit Write Enable Input
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); // End of RAMB16BWE_S36_S36_inst instantiation
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endmodule // bootram
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