mirror of
https://github.com/fairwaves/UHD-Fairwaves.git
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140 lines
4.2 KiB
Verilog
140 lines
4.2 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module double_buffer
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#(parameter BUF_SIZE = 9)
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(input clk, input reset, input clear,
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// Random access interface to RAM
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input access_we,
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input access_stb,
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output access_ok,
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input access_done,
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input access_skip_read,
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input [BUF_SIZE-1:0] access_adr,
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output [BUF_SIZE-1:0] access_len,
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input [35:0] access_dat_i,
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output [35:0] access_dat_o,
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// Write FIFO Interface
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input [35:0] data_i,
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input src_rdy_i,
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output dst_rdy_o,
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// Read FIFO Interface
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output [35:0] data_o,
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output src_rdy_o,
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input dst_rdy_i
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);
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wire [35:0] data_o_0, data_o_1;
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wire read, read_ok, read_ptr, read_done;
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wire write, write_ok, write_ptr, write_done;
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wire [BUF_SIZE-1:0] rw0_adr, rw1_adr;
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reg [BUF_SIZE-1:0] read_adr, write_adr;
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reg [BUF_SIZE-1:0] len0, len1;
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assign data_o = read_ptr ? data_o_1 : data_o_0;
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assign rw0_adr = (write_ok & ~write_ptr) ? write_adr : read_adr;
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assign rw1_adr = (write_ok & write_ptr) ? write_adr : read_adr;
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wire [35:0] access_dat_o_0, access_dat_o_1;
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wire access_ptr;
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assign access_dat_o = access_ptr? access_dat_o_1 : access_dat_o_0;
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dbsm dbsm
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(.clk(clk), .reset(reset), .clear(clear),
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.write_ok(write_ok), .write_ptr(write_ptr), .write_done(write_done),
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.access_ok(access_ok), .access_ptr(access_ptr), .access_done(access_done), .access_skip_read(access_skip_read),
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.read_ok(read_ok), .read_ptr(read_ptr), .read_done(read_done));
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// Port A for random access, Port B for FIFO read and write
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ram_2port #(.DWIDTH(36),.AWIDTH(BUF_SIZE)) buffer0
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(.clka(clk),.ena(access_stb & access_ok & (access_ptr == 0)),.wea(access_we),
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.addra(access_adr),.dia(access_dat_i),.doa(access_dat_o_0),
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.clkb(clk),.enb((read & read_ok & ~read_ptr)|(write & write_ok & ~write_ptr) ),.web(write&write_ok&~write_ptr),
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.addrb(rw0_adr),.dib(data_i),.dob(data_o_0));
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ram_2port #(.DWIDTH(36),.AWIDTH(BUF_SIZE)) buffer1
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(.clka(clk),.ena(access_stb & access_ok & (access_ptr == 1)),.wea(access_we),
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.addra(access_adr),.dia(access_dat_i),.doa(access_dat_o_1),
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.clkb(clk),.enb((read & read_ok & read_ptr)|(write & write_ok & write_ptr) ),.web(write&write_ok&write_ptr),
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.addrb(rw1_adr),.dib(data_i),.dob(data_o_1));
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// Write into buffers
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assign dst_rdy_o = write_ok;
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assign write = src_rdy_i & write_ok;
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assign write_done = write & data_i[33]; // done
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always @(posedge clk)
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if(reset | clear)
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write_adr <= 0;
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else
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if(write_done)
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begin
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write_adr <= 0;
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if(write_ptr)
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len1 <= write_adr + 1;
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else
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len0 <= write_adr + 1;
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end
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else if(write)
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write_adr <= write_adr + 1;
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assign access_len = access_ptr ? len1 : len0;
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reg [1:0] read_state;
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localparam IDLE = 0;
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localparam PRE_READ = 1;
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localparam READING = 2;
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always @(posedge clk)
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if(reset | clear)
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begin
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read_state <= IDLE;
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read_adr <= 0;
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end
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else
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case(read_state)
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IDLE :
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begin
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read_adr <= 0;
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if(read_ok)
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read_state <= PRE_READ;
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end
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PRE_READ :
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begin
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read_state <= READING;
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read_adr <= 1;
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end
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READING :
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if(dst_rdy_i)
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begin
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read_adr <= read_adr + 1;
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if(data_o[33])
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read_state <= IDLE;
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end
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endcase // case (read_state)
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assign read = ~((read_state==READING)& ~dst_rdy_i);
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assign read_done = data_o[33] & dst_rdy_i & src_rdy_o;
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assign src_rdy_o = (read_state == READING);
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endmodule // double_buffer
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