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100 lines
3.1 KiB
Verilog
100 lines
3.1 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// Dual ported RAM
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// Addresses are byte-oriented, so botton 2 address bits are ignored.
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// AWIDTH of 13 allows you to address 8K bytes.
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// For Spartan 3, if the total RAM size is not a multiple of 8K then BRAM space is wasted
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// RAM_SIZE parameter allows odd-sized RAMs, like 24K
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module dpram32 #(parameter AWIDTH=15,
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parameter RAM_SIZE=16384)
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(input clk,
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input [AWIDTH-1:0] adr1_i,
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input [31:0] dat1_i,
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output reg [31:0] dat1_o,
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input we1_i,
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input en1_i,
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input [3:0] sel1_i,
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input [AWIDTH-1:0] adr2_i,
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input [31:0] dat2_i,
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output reg [31:0] dat2_o,
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input we2_i,
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input en2_i,
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input [3:0] sel2_i );
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reg [7:0] ram0 [0:(RAM_SIZE/4)-1];
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reg [7:0] ram1 [0:(RAM_SIZE/4)-1];
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reg [7:0] ram2 [0:(RAM_SIZE/4)-1];
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reg [7:0] ram3 [0:(RAM_SIZE/4)-1];
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// This is how we used to size the RAM -->
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// reg [7:0] ram3 [0:(1<<(AWIDTH-2))-1];
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// Port 1
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always @(posedge clk)
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if(en1_i) dat1_o[31:24] <= ram3[adr1_i[AWIDTH-1:2]];
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always @(posedge clk)
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if(en1_i) dat1_o[23:16] <= ram2[adr1_i[AWIDTH-1:2]];
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always @(posedge clk)
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if(en1_i) dat1_o[15:8] <= ram1[adr1_i[AWIDTH-1:2]];
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always @(posedge clk)
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if(en1_i) dat1_o[7:0] <= ram0[adr1_i[AWIDTH-1:2]];
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always @(posedge clk)
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if(we1_i & en1_i & sel1_i[3])
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ram3[adr1_i[AWIDTH-1:2]] <= dat1_i[31:24];
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always @(posedge clk)
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if(we1_i & en1_i & sel1_i[2])
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ram2[adr1_i[AWIDTH-1:2]] <= dat1_i[23:16];
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always @(posedge clk)
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if(we1_i & en1_i & sel1_i[1])
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ram1[adr1_i[AWIDTH-1:2]] <= dat1_i[15:8];
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always @(posedge clk)
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if(we1_i & en1_i & sel1_i[0])
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ram0[adr1_i[AWIDTH-1:2]] <= dat1_i[7:0];
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// Port 2
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always @(posedge clk)
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if(en2_i) dat2_o[31:24] <= ram3[adr2_i[AWIDTH-1:2]];
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always @(posedge clk)
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if(en2_i) dat2_o[23:16] <= ram2[adr2_i[AWIDTH-1:2]];
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always @(posedge clk)
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if(en2_i) dat2_o[15:8] <= ram1[adr2_i[AWIDTH-1:2]];
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always @(posedge clk)
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if(en2_i) dat2_o[7:0] <= ram0[adr2_i[AWIDTH-1:2]];
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always @(posedge clk)
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if(we2_i & en2_i & sel2_i[3])
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ram3[adr2_i[AWIDTH-1:2]] <= dat2_i[31:24];
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always @(posedge clk)
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if(we2_i & en2_i & sel2_i[2])
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ram2[adr2_i[AWIDTH-1:2]] <= dat2_i[23:16];
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always @(posedge clk)
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if(we2_i & en2_i & sel2_i[1])
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ram1[adr2_i[AWIDTH-1:2]] <= dat2_i[15:8];
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always @(posedge clk)
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if(we2_i & en2_i & sel2_i[0])
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ram0[adr2_i[AWIDTH-1:2]] <= dat2_i[7:0];
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endmodule // dpram32
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