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47 lines
1.4 KiB
Verilog
47 lines
1.4 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module gray_send
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#(parameter WIDTH = 8)
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(input clk_in, input [WIDTH-1:0] addr_in,
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input clk_out, output reg [WIDTH-1:0] addr_out);
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reg [WIDTH-1:0] gray_clkin, gray_clkout, gray_clkout_d1;
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wire [WIDTH-1:0] gray, bin;
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bin2gray #(.WIDTH(WIDTH)) b2g (.bin(addr_in), .gray(gray) );
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always @(posedge clk_in)
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gray_clkin <= gray;
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always @(posedge clk_out)
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gray_clkout <= gray_clkin;
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always @(posedge clk_out)
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gray_clkout_d1 <= gray_clkout;
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gray2bin #(.WIDTH(WIDTH)) g2b (.gray(gray_clkout_d1), .bin(bin) );
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// FIXME we may not need the next register, but it may help timing
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always @(posedge clk_out)
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addr_out <= bin;
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endmodule // gray_send
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