mirror of
https://github.com/fairwaves/UHD-Fairwaves.git
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94 lines
3.6 KiB
Verilog
94 lines
3.6 KiB
Verilog
// Modified from code originally by Richard Herveille, his copyright is below
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// OpenCores Simple General Purpose IO core ////
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//// ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2002 Richard Herveille ////
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//// richard@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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module nsgpio
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(input clk_i, input rst_i,
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input cyc_i, input stb_i, input [4:0] adr_i, input we_i, input [31:0] dat_i,
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output reg [31:0] dat_o, output reg ack_o,
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input tx, input rx, inout [31:0] gpio
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);
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integer n;
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reg [31:0] ddr;
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reg [31:0] idle_out, rx_out, tx_out, fdx_out;
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reg [31:0] rgpio, igpio;
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wire wb_acc = cyc_i & stb_i; // WISHBONE access
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wire wb_wr = wb_acc & we_i; // WISHBONE write access
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always @(posedge clk_i or posedge rst_i)
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if (rst_i)
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ddr <= 0;
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else if (wb_wr)
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case( adr_i[4:2] )
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3'b000 :
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idle_out <= dat_i;
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3'b001 :
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rx_out <= dat_i;
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3'b010 :
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tx_out <= dat_i;
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3'b011 :
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fdx_out <= dat_i;
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3'b100 :
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ddr <= dat_i;
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endcase // case ( adr_i[4:2] )
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always @(posedge clk_i)
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dat_o <= gpio;
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always @(posedge clk_i or posedge rst_i)
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if (rst_i)
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ack_o <= 1'b0;
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else
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ack_o <= wb_acc & !ack_o;
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always @(posedge clk_i)
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case({tx,rx})
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2'b00 : rgpio <= idle_out;
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2'b01 : rgpio <= rx_out;
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2'b10 : rgpio <= tx_out;
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2'b11 : rgpio <= fdx_out;
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endcase // case ({tx,rx})
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always @*
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for(n=0;n<32;n=n+1)
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igpio[n] <= ddr[n] ? rgpio[n] : 1'bz;
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assign gpio = igpio;
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endmodule
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