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62 lines
2.9 KiB
Verilog
62 lines
2.9 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module priority_enc
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(input [31:0] in,
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output reg [31:0] out);
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always @*
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casex(in)
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32'b1xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 31;
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32'b01xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 30;
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32'b001x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 29;
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32'b0001_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 28;
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32'b0000_1xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 27;
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32'b0000_01xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 26;
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32'b0000_001x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 25;
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32'b0000_0001_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 24;
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32'b0000_0000_1xxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 23;
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32'b0000_0000_01xx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 22;
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32'b0000_0000_001x_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 21;
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32'b0000_0000_0001_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 20;
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32'b0000_0000_0000_1xxx_xxxx_xxxx_xxxx_xxxx : out <= 19;
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32'b0000_0000_0000_01xx_xxxx_xxxx_xxxx_xxxx : out <= 18;
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32'b0000_0000_0000_001x_xxxx_xxxx_xxxx_xxxx : out <= 17;
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32'b0000_0000_0000_0001_xxxx_xxxx_xxxx_xxxx : out <= 16;
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32'b0000_0000_0000_0000_1xxx_xxxx_xxxx_xxxx : out <= 15;
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32'b0000_0000_0000_0000_01xx_xxxx_xxxx_xxxx : out <= 14;
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32'b0000_0000_0000_0000_001x_xxxx_xxxx_xxxx : out <= 13;
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32'b0000_0000_0000_0000_0001_xxxx_xxxx_xxxx : out <= 12;
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32'b0000_0000_0000_0000_0000_1xxx_xxxx_xxxx : out <= 11;
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32'b0000_0000_0000_0000_0000_01xx_xxxx_xxxx : out <= 10;
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32'b0000_0000_0000_0000_0000_001x_xxxx_xxxx : out <= 9;
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32'b0000_0000_0000_0000_0000_0001_xxxx_xxxx : out <= 8;
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32'b0000_0000_0000_0000_0000_0000_1xxx_xxxx : out <= 7;
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32'b0000_0000_0000_0000_0000_0000_01xx_xxxx : out <= 6;
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32'b0000_0000_0000_0000_0000_0000_001x_xxxx : out <= 5;
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32'b0000_0000_0000_0000_0000_0000_0001_xxxx : out <= 4;
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32'b0000_0000_0000_0000_0000_0000_0000_1xxx : out <= 3;
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32'b0000_0000_0000_0000_0000_0000_0000_01xx : out <= 2;
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32'b0000_0000_0000_0000_0000_0000_0000_001x : out <= 1;
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32'b0000_0000_0000_0000_0000_0000_0000_0001 : out <= 0;
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32'b0000_0000_0000_0000_0000_0000_0000_0000 : out <= 32'hFFFF_FFFF;
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default : out <= 32'hFFFF_FFFF;
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endcase // casex (in)
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endmodule // priority_enc
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