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138 lines
4.8 KiB
Verilog
138 lines
4.8 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module ram_2port_mixed_width
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(input clk16,
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input en16,
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input we16,
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input [10:0] addr16,
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input [15:0] di16,
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output [15:0] do16,
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input clk32,
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input en32,
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input we32,
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input [9:0] addr32,
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input [31:0] di32,
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output [31:0] do32);
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wire en32a = en32 & ~addr32[9];
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wire en32b = en32 & addr32[9];
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wire en16a = en16 & ~addr16[10];
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wire en16b = en16 & addr16[10];
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wire [31:0] do32a, do32b;
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wire [15:0] do16a, do16b;
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assign do32 = addr32[9] ? do32b : do32a;
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assign do16 = addr16[10] ? do16b : do16a;
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RAMB16BWE_S36_S18 #(.INIT_A(36'h000000000),
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.INIT_B(18'h00000),
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.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
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.SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
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.SRVAL_B(18'h00000), // Port B output value upon SSR assertion
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.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
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.WRITE_MODE_B("WRITE_FIRST") // WRITE_FIRST, READ_FIRST or NO_CHANGE
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)
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RAMB16BWE_S36_S18_0 (.DOA(do32a), // Port A 32-bit Data Output
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.DOB(do16a), // Port B 16-bit Data Output
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.DOPA(), // Port A 4-bit Parity Output
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.DOPB(), // Port B 2-bit Parity Output
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.ADDRA(addr32[8:0]), // Port A 9-bit Address Input
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.ADDRB(addr16[9:0]), // Port B 10-bit Address Input
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.CLKA(clk32), // Port A 1-bit Clock
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.CLKB(clk16), // Port B 1-bit Clock
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.DIA(di32), // Port A 32-bit Data Input
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.DIB(di16), // Port B 16-bit Data Input
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.DIPA(0), // Port A 4-bit parity Input
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.DIPB(0), // Port-B 2-bit parity Input
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.ENA(en32a), // Port A 1-bit RAM Enable Input
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.ENB(en16a), // Port B 1-bit RAM Enable Input
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.SSRA(0), // Port A 1-bit Synchronous Set/Reset Input
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.SSRB(0), // Port B 1-bit Synchronous Set/Reset Input
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.WEA({4{we32}}), // Port A 4-bit Write Enable Input
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.WEB({2{we16}}) // Port B 2-bit Write Enable Input
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);
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RAMB16BWE_S36_S18 #(.INIT_A(36'h000000000),
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.INIT_B(18'h00000),
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.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
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.SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
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.SRVAL_B(18'h00000), // Port B output value upon SSR assertion
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.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
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.WRITE_MODE_B("WRITE_FIRST") // WRITE_FIRST, READ_FIRST or NO_CHANGE
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)
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RAMB16BWE_S36_S18_1 (.DOA(do32b), // Port A 32-bit Data Output
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.DOB(do16b), // Port B 16-bit Data Output
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.DOPA(), // Port A 4-bit Parity Output
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.DOPB(), // Port B 2-bit Parity Output
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.ADDRA(addr32[8:0]), // Port A 9-bit Address Input
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.ADDRB(addr16[9:0]), // Port B 10-bit Address Input
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.CLKA(clk32), // Port A 1-bit Clock
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.CLKB(clk16), // Port B 1-bit Clock
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.DIA(di32), // Port A 32-bit Data Input
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.DIB(di16), // Port B 16-bit Data Input
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.DIPA(0), // Port A 4-bit parity Input
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.DIPB(0), // Port-B 2-bit parity Input
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.ENA(en32b), // Port A 1-bit RAM Enable Input
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.ENB(en16b), // Port B 1-bit RAM Enable Input
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.SSRA(0), // Port A 1-bit Synchronous Set/Reset Input
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.SSRB(0), // Port B 1-bit Synchronous Set/Reset Input
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.WEA({4{we32}}), // Port A 4-bit Write Enable Input
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.WEB({2{we16}}) // Port B 2-bit Write Enable Input
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);
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endmodule // ram_2port_mixed_width
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// ISE 10.1.03 chokes on the following
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/*
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reg [31:0] ram [(1<<AWIDTH)-1:0];
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integer i;
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initial
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for(i=0;i<512;i=i+1)
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ram[i] <= 32'b0;
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always @(posedge clk16)
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if (en16)
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begin
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if (we16)
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if(addr16[0])
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ram[addr16[10:1]][15:0] <= di16;
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else
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ram[addr16[10:1]][31:16] <= di16;
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do16 <= addr16[0] ? ram[addr16[10:1]][15:0] : ram[addr16[10:1]][31:16];
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end
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always @(posedge clk32)
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if (en32)
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begin
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if (we32)
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ram[addr32] <= di32;
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do32 <= ram[addr32];
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end
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endmodule // ram_2port_mixed_width
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*/
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