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94 lines
2.7 KiB
Verilog
94 lines
2.7 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// Wishbone module for spi communications with an SD Card
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// The programming interface is simple --
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// Write the desired clock divider to address 1 (should be 1 or higher)
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// Status is in address 0. A 1 indicates the last transaction is done and it is safe to
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// send another
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// Writing a byte to address 2 sends that byte over SPI. When it is done,
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// status (addr 0) goes high again, and the received byte can be read from address 3.
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module sd_spi_wb
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(input clk,
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input rst,
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// SD Card interface
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output sd_clk,
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output sd_csn,
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output sd_mosi,
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input sd_miso,
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input wb_cyc_i,
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input wb_stb_i,
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input wb_we_i,
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input [1:0] wb_adr_i,
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input [7:0] wb_dat_i,
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output reg [7:0] wb_dat_o,
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output reg wb_ack_o);
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localparam ADDR_STATUS = 0;
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localparam ADDR_CLKDIV = 1;
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localparam ADDR_WRITE = 2;
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localparam ADDR_READ = 3;
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wire [7:0] status, rcv_dat;
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reg [7:0] clkdiv;
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wire ready;
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reg ack_d1;
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reg cs_reg;
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assign sd_csn = ~cs_reg; // FIXME
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always @(posedge clk)
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if(rst) ack_d1 <= 0;
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else ack_d1 <= wb_ack_o;
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always @(posedge clk)
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if(rst) wb_ack_o <= 0;
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else wb_ack_o <= wb_cyc_i & wb_stb_i & ~ack_d1;
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always @(posedge clk)
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case(wb_adr_i)
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ADDR_STATUS : wb_dat_o <= {7'd0,ready};
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ADDR_CLKDIV : wb_dat_o <= clkdiv;
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ADDR_READ : wb_dat_o <= rcv_dat;
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default : wb_dat_o <= 0;
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endcase // case(wb_adr_i)
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always @(posedge clk)
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if(rst)
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begin
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clkdiv <= 200;
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cs_reg <= 0;
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end
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else if(wb_we_i & wb_stb_i & wb_cyc_i & wb_ack_o)
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case(wb_adr_i)
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ADDR_STATUS : cs_reg <= wb_dat_i;
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ADDR_CLKDIV : clkdiv <= wb_dat_i;
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endcase // case(wb_adr_i)
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wire go = wb_we_i & wb_stb_i & wb_cyc_i & wb_ack_o & (wb_adr_i == ADDR_WRITE);
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sd_spi sd_spi(.clk(clk),.rst(rst),
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.sd_clk(sd_clk),.sd_mosi(sd_mosi),.sd_miso(sd_miso),
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.clk_div(clkdiv),.send_dat(wb_dat_i),.rcv_dat(rcv_dat),
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.go(go),.ready(ready) );
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endmodule // sd_spi_wb
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