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72 lines
2.0 KiB
Verilog
72 lines
2.0 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// Grab settings off the wishbone bus, send them out to settings bus
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// 16 bits little endian, but all registers need to be written 32 bits at a time.
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// This means that you write the low 16 bits first and then the high 16 bits.
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// The setting regs are strobed when the high 16 bits are written
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module settings_bus_16LE
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#(parameter AWIDTH=16, RWIDTH=8)
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(input wb_clk,
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input wb_rst,
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input [AWIDTH-1:0] wb_adr_i,
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input [15:0] wb_dat_i,
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input wb_stb_i,
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input wb_we_i,
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output reg wb_ack_o,
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output strobe,
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output reg [7:0] addr,
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output reg [31:0] data);
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reg stb_int;
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always @(posedge wb_clk)
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if(wb_rst)
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begin
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stb_int <= 1'b0;
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addr <= 8'd0;
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data <= 32'd0;
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end
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else if(wb_we_i & wb_stb_i)
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begin
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addr <= wb_adr_i[RWIDTH+1:2]; // Zero pad high bits
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if(wb_adr_i[1])
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begin
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stb_int <= 1'b1; // We now have both halves
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data[31:16] <= wb_dat_i;
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end
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else
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begin
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stb_int <= 1'b0; // Don't strobe, we need other half
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data[15:0] <= wb_dat_i;
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end
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end
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else
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stb_int <= 1'b0;
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always @(posedge wb_clk)
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if(wb_rst)
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wb_ack_o <= 0;
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else
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wb_ack_o <= wb_stb_i & ~wb_ack_o;
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assign strobe = stb_int & wb_ack_o;
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endmodule // settings_bus_16LE
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