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75 lines
1.8 KiB
Verilog
75 lines
1.8 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module system_control_tb();
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reg aux_clk, clk_fpga;
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wire wb_clk, dsp_clk;
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wire wb_rst, dsp_rst, rl_rst, proc_rst;
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reg rl_done, clock_ready;
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initial aux_clk = 1'b0;
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always #25 aux_clk = ~aux_clk;
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initial clk_fpga = 1'b0;
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initial clock_ready = 1'b0;
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initial
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begin
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@(negedge proc_rst);
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#1003 clock_ready <= 1'b1;
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end
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always #7 clk_fpga = ~clk_fpga;
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initial begin
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$dumpfile("system_control_tb.vcd");
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$dumpvars(0,system_control_tb);
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end
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initial #10000 $finish;
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initial
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begin
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@(negedge rl_rst);
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rl_done <= 1'b0;
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#1325 rl_done <= 1'b1;
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end
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initial
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begin
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@(negedge proc_rst);
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clock_ready <= 1'b0;
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#327 clock_ready <= 1'b1;
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end
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system_control
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system_control(.aux_clk_i(aux_clk),.clk_fpga_i(clk_fpga),
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.dsp_clk_o(dsp_clk),.wb_clk_o(wb_clk),
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.ram_loader_rst_o(rl_rst),
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.processor_rst_o(proc_rst),
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.wb_rst_o(wb_rst),
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.dsp_rst_o(dsp_rst),
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.ram_loader_done_i(rl_done),
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.clock_ready_i(clock_ready),
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.debug_o());
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endmodule // system_control_tb
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