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465 lines
17 KiB
Verilog
465 lines
17 KiB
Verilog
/////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE Connection Bus Top Level ////
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//// ////
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//// ////
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//// Original Author: Johny Chi ////
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//// chisuhua@yahoo.com.cn ////
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//// Modified By Matt Ettus, matt@ettus.com ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000, 2007 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// Up to 8 slaves share a Wishbone Bus connection to 1 master
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module wb_1master
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#(parameter decode_w = 8, // address decode width
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parameter s0_addr = 8'h0, // slave 0 address
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parameter s0_mask = 8'h0, // slave 0 don't cares
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parameter s1_addr = 8'h0, // slave 1 address
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parameter s1_mask = 8'h0, // slave 1 don't cares
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parameter s2_addr = 8'h0, // slave 2 address
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parameter s2_mask = 8'h0, // slave 2 don't cares
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parameter s3_addr = 8'h0, // slave 3 address
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parameter s3_mask = 8'h0, // slave 3 don't cares
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parameter s4_addr = 8'h0, // slave 4 address
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parameter s4_mask = 8'h0, // slave 4 don't cares
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parameter s5_addr = 8'h0, // slave 5 address
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parameter s5_mask = 8'h0, // slave 5 don't cares
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parameter s6_addr = 8'h0, // slave 6 address
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parameter s6_mask = 8'h0, // slave 6 don't cares
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parameter s7_addr = 8'h0, // slave 7 address
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parameter s7_mask = 8'h0, // slave 7 don't cares
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parameter s8_addr = 8'h0, // slave 8 address
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parameter s8_mask = 8'h0, // slave 8 don't cares
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parameter s9_addr = 8'h0, // slave 9 address
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parameter s9_mask = 8'h0, // slave 9 don't cares
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parameter sa_addr = 8'h0, // slave a address
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parameter sa_mask = 8'h0, // slave a don't cares
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parameter sb_addr = 8'h0, // slave b address
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parameter sb_mask = 8'h0, // slave b don't cares
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parameter sc_addr = 8'h0, // slave c address
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parameter sc_mask = 8'h0, // slave c don't cares
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parameter sd_addr = 8'h0, // slave d address
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parameter sd_mask = 8'h0, // slave d don't cares
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parameter se_addr = 8'h0, // slave e address
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parameter se_mask = 8'h0, // slave e don't cares
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parameter sf_addr = 8'h0, // slave f address
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parameter sf_mask = 8'h0, // slave f don't cares
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parameter dw = 32, // Data bus Width
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parameter aw = 32, // Address bus Width
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parameter sw = 4) // Number of Select Lines
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(input clk_i,
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input rst_i,
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// Master Interface
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input [dw-1:0] m0_dat_i,
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output [dw-1:0] m0_dat_o,
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input [aw-1:0] m0_adr_i,
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input [sw-1:0] m0_sel_i,
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input m0_we_i,
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input m0_cyc_i,
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input m0_stb_i,
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output m0_ack_o,
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output m0_err_o,
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output m0_rty_o,
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// Slave Interfaces
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input [dw-1:0] s0_dat_i,
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output [dw-1:0] s0_dat_o,
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output [aw-1:0] s0_adr_o,
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output [sw-1:0] s0_sel_o,
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output s0_we_o,
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output s0_cyc_o,
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output s0_stb_o,
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input s0_ack_i,
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input s0_err_i,
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input s0_rty_i,
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input [dw-1:0] s1_dat_i,
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output [dw-1:0] s1_dat_o,
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output [aw-1:0] s1_adr_o,
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output [sw-1:0] s1_sel_o,
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output s1_we_o,
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output s1_cyc_o,
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output s1_stb_o,
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input s1_ack_i,
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input s1_err_i,
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input s1_rty_i,
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input [dw-1:0] s2_dat_i,
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output [dw-1:0] s2_dat_o,
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output [aw-1:0] s2_adr_o,
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output [sw-1:0] s2_sel_o,
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output s2_we_o,
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output s2_cyc_o,
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output s2_stb_o,
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input s2_ack_i,
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input s2_err_i,
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input s2_rty_i,
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input [dw-1:0] s3_dat_i,
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output [dw-1:0] s3_dat_o,
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output [aw-1:0] s3_adr_o,
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output [sw-1:0] s3_sel_o,
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output s3_we_o,
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output s3_cyc_o,
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output s3_stb_o,
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input s3_ack_i,
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input s3_err_i,
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input s3_rty_i,
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input [dw-1:0] s4_dat_i,
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output [dw-1:0] s4_dat_o,
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output [aw-1:0] s4_adr_o,
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output [sw-1:0] s4_sel_o,
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output s4_we_o,
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output s4_cyc_o,
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output s4_stb_o,
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input s4_ack_i,
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input s4_err_i,
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input s4_rty_i,
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input [dw-1:0] s5_dat_i,
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output [dw-1:0] s5_dat_o,
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output [aw-1:0] s5_adr_o,
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output [sw-1:0] s5_sel_o,
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output s5_we_o,
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output s5_cyc_o,
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output s5_stb_o,
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input s5_ack_i,
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input s5_err_i,
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input s5_rty_i,
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input [dw-1:0] s6_dat_i,
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output [dw-1:0] s6_dat_o,
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output [aw-1:0] s6_adr_o,
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output [sw-1:0] s6_sel_o,
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output s6_we_o,
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output s6_cyc_o,
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output s6_stb_o,
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input s6_ack_i,
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input s6_err_i,
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input s6_rty_i,
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input [dw-1:0] s7_dat_i,
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output [dw-1:0] s7_dat_o,
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output [aw-1:0] s7_adr_o,
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output [sw-1:0] s7_sel_o,
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output s7_we_o,
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output s7_cyc_o,
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output s7_stb_o,
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input s7_ack_i,
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input s7_err_i,
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input s7_rty_i,
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input [dw-1:0] s8_dat_i,
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output [dw-1:0] s8_dat_o,
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output [aw-1:0] s8_adr_o,
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output [sw-1:0] s8_sel_o,
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output s8_we_o,
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output s8_cyc_o,
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output s8_stb_o,
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input s8_ack_i,
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input s8_err_i,
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input s8_rty_i,
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input [dw-1:0] s9_dat_i,
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output [dw-1:0] s9_dat_o,
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output [aw-1:0] s9_adr_o,
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output [sw-1:0] s9_sel_o,
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output s9_we_o,
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output s9_cyc_o,
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output s9_stb_o,
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input s9_ack_i,
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input s9_err_i,
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input s9_rty_i,
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input [dw-1:0] sa_dat_i,
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output [dw-1:0] sa_dat_o,
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output [aw-1:0] sa_adr_o,
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output [sw-1:0] sa_sel_o,
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output sa_we_o,
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output sa_cyc_o,
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output sa_stb_o,
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input sa_ack_i,
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input sa_err_i,
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input sa_rty_i,
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input [dw-1:0] sb_dat_i,
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output [dw-1:0] sb_dat_o,
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output [aw-1:0] sb_adr_o,
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output [sw-1:0] sb_sel_o,
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output sb_we_o,
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output sb_cyc_o,
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output sb_stb_o,
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input sb_ack_i,
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input sb_err_i,
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input sb_rty_i,
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input [dw-1:0] sc_dat_i,
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output [dw-1:0] sc_dat_o,
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output [aw-1:0] sc_adr_o,
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output [sw-1:0] sc_sel_o,
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output sc_we_o,
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output sc_cyc_o,
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output sc_stb_o,
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input sc_ack_i,
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input sc_err_i,
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input sc_rty_i,
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input [dw-1:0] sd_dat_i,
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output [dw-1:0] sd_dat_o,
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output [aw-1:0] sd_adr_o,
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output [sw-1:0] sd_sel_o,
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output sd_we_o,
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output sd_cyc_o,
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output sd_stb_o,
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input sd_ack_i,
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input sd_err_i,
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input sd_rty_i,
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input [dw-1:0] se_dat_i,
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output [dw-1:0] se_dat_o,
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output [aw-1:0] se_adr_o,
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output [sw-1:0] se_sel_o,
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output se_we_o,
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output se_cyc_o,
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output se_stb_o,
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input se_ack_i,
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input se_err_i,
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input se_rty_i,
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input [dw-1:0] sf_dat_i,
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output [dw-1:0] sf_dat_o,
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output [aw-1:0] sf_adr_o,
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output [sw-1:0] sf_sel_o,
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output sf_we_o,
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output sf_cyc_o,
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output sf_stb_o,
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input sf_ack_i,
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input sf_err_i,
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input sf_rty_i
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);
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// ////////////////////////////////////////////////////////////////
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//
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// Local wires
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//
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wire [15:0] ssel_dec;
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reg [dw-1:0] i_dat_s; // internal share bus , slave data to master
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// Master output Interface
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assign m0_dat_o = i_dat_s;
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always @*
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case(ssel_dec)
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1 : i_dat_s <= s0_dat_i;
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2 : i_dat_s <= s1_dat_i;
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4 : i_dat_s <= s2_dat_i;
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8 : i_dat_s <= s3_dat_i;
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16 : i_dat_s <= s4_dat_i;
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32 : i_dat_s <= s5_dat_i;
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64 : i_dat_s <= s6_dat_i;
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128 : i_dat_s <= s7_dat_i;
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256 : i_dat_s <= s8_dat_i;
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512 : i_dat_s <= s9_dat_i;
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1024 : i_dat_s <= sa_dat_i;
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2048 : i_dat_s <= sb_dat_i;
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4096 : i_dat_s <= sc_dat_i;
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8192 : i_dat_s <= sd_dat_i;
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16384 : i_dat_s <= se_dat_i;
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32768 : i_dat_s <= sf_dat_i;
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default : i_dat_s <= s0_dat_i;
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endcase // case(ssel_dec)
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assign {m0_ack_o, m0_err_o, m0_rty_o}
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= {s0_ack_i | s1_ack_i | s2_ack_i | s3_ack_i | s4_ack_i | s5_ack_i | s6_ack_i | s7_ack_i |
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s8_ack_i | s9_ack_i | sa_ack_i | sb_ack_i | sc_ack_i | sd_ack_i | se_ack_i | sf_ack_i ,
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s0_err_i | s1_err_i | s2_err_i | s3_err_i | s4_err_i | s5_err_i | s6_err_i | s7_err_i |
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s8_err_i | s9_err_i | sa_err_i | sb_err_i | sc_err_i | sd_err_i | se_err_i | sf_err_i ,
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s0_rty_i | s1_rty_i | s2_rty_i | s3_rty_i | s4_rty_i | s5_rty_i | s6_rty_i | s7_rty_i |
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s8_rty_i | s9_rty_i | sa_rty_i | sb_rty_i | sc_rty_i | sd_rty_i | se_rty_i | sf_rty_i };
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// Slave output interfaces
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assign s0_adr_o = m0_adr_i;
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assign s0_sel_o = m0_sel_i;
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assign s0_dat_o = m0_dat_i;
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assign s0_we_o = m0_we_i;
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assign s0_cyc_o = m0_cyc_i;
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assign s0_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[0];
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assign s1_adr_o = m0_adr_i;
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assign s1_sel_o = m0_sel_i;
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assign s1_dat_o = m0_dat_i;
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assign s1_we_o = m0_we_i;
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assign s1_cyc_o = m0_cyc_i;
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assign s1_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[1];
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assign s2_adr_o = m0_adr_i;
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assign s2_sel_o = m0_sel_i;
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assign s2_dat_o = m0_dat_i;
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assign s2_we_o = m0_we_i;
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assign s2_cyc_o = m0_cyc_i;
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assign s2_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[2];
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assign s3_adr_o = m0_adr_i;
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assign s3_sel_o = m0_sel_i;
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assign s3_dat_o = m0_dat_i;
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assign s3_we_o = m0_we_i;
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assign s3_cyc_o = m0_cyc_i;
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assign s3_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[3];
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assign s4_adr_o = m0_adr_i;
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assign s4_sel_o = m0_sel_i;
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assign s4_dat_o = m0_dat_i;
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assign s4_we_o = m0_we_i;
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assign s4_cyc_o = m0_cyc_i;
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assign s4_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[4];
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assign s5_adr_o = m0_adr_i;
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assign s5_sel_o = m0_sel_i;
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assign s5_dat_o = m0_dat_i;
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assign s5_we_o = m0_we_i;
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assign s5_cyc_o = m0_cyc_i;
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assign s5_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[5];
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assign s6_adr_o = m0_adr_i;
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assign s6_sel_o = m0_sel_i;
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assign s6_dat_o = m0_dat_i;
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assign s6_we_o = m0_we_i;
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assign s6_cyc_o = m0_cyc_i;
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assign s6_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[6];
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assign s7_adr_o = m0_adr_i;
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assign s7_sel_o = m0_sel_i;
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assign s7_dat_o = m0_dat_i;
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assign s7_we_o = m0_we_i;
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assign s7_cyc_o = m0_cyc_i;
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assign s7_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[7];
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assign s8_adr_o = m0_adr_i;
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assign s8_sel_o = m0_sel_i;
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assign s8_dat_o = m0_dat_i;
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assign s8_we_o = m0_we_i;
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assign s8_cyc_o = m0_cyc_i;
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assign s8_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[8];
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assign s9_adr_o = m0_adr_i;
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assign s9_sel_o = m0_sel_i;
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assign s9_dat_o = m0_dat_i;
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assign s9_we_o = m0_we_i;
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assign s9_cyc_o = m0_cyc_i;
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assign s9_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[9];
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assign sa_adr_o = m0_adr_i;
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assign sa_sel_o = m0_sel_i;
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assign sa_dat_o = m0_dat_i;
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assign sa_we_o = m0_we_i;
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assign sa_cyc_o = m0_cyc_i;
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assign sa_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[10];
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assign sb_adr_o = m0_adr_i;
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assign sb_sel_o = m0_sel_i;
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assign sb_dat_o = m0_dat_i;
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assign sb_we_o = m0_we_i;
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assign sb_cyc_o = m0_cyc_i;
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assign sb_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[11];
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assign sc_adr_o = m0_adr_i;
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assign sc_sel_o = m0_sel_i;
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assign sc_dat_o = m0_dat_i;
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assign sc_we_o = m0_we_i;
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assign sc_cyc_o = m0_cyc_i;
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assign sc_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[12];
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assign sd_adr_o = m0_adr_i;
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assign sd_sel_o = m0_sel_i;
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assign sd_dat_o = m0_dat_i;
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assign sd_we_o = m0_we_i;
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assign sd_cyc_o = m0_cyc_i;
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assign sd_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[13];
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assign se_adr_o = m0_adr_i;
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assign se_sel_o = m0_sel_i;
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assign se_dat_o = m0_dat_i;
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assign se_we_o = m0_we_i;
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assign se_cyc_o = m0_cyc_i;
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assign se_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[14];
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assign sf_adr_o = m0_adr_i;
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assign sf_sel_o = m0_sel_i;
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assign sf_dat_o = m0_dat_i;
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assign sf_we_o = m0_we_i;
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assign sf_cyc_o = m0_cyc_i;
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assign sf_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[15];
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// Address decode logic
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// WARNING -- must make sure these are mutually exclusive!
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assign ssel_dec[0] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s0_addr) & s0_mask);
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assign ssel_dec[1] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s1_addr) & s1_mask);
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assign ssel_dec[2] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s2_addr) & s2_mask);
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assign ssel_dec[3] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s3_addr) & s3_mask);
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assign ssel_dec[4] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s4_addr) & s4_mask);
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assign ssel_dec[5] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s5_addr) & s5_mask);
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assign ssel_dec[6] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s6_addr) & s6_mask);
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assign ssel_dec[7] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s7_addr) & s7_mask);
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assign ssel_dec[8] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s8_addr) & s8_mask);
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assign ssel_dec[9] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s9_addr) & s9_mask);
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assign ssel_dec[10] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sa_addr) & sa_mask);
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assign ssel_dec[11] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sb_addr) & sb_mask);
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assign ssel_dec[12] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sc_addr) & sc_mask);
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assign ssel_dec[13] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sd_addr) & sd_mask);
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assign ssel_dec[14] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ se_addr) & se_mask);
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assign ssel_dec[15] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sf_addr) & sf_mask);
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/*
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assign ssel_dec[0] = (m0_adr_i[aw -1 : aw - decode_w ] == s0_addr);
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assign ssel_dec[1] = (m0_adr_i[aw -1 : aw - decode_w ] == s1_addr);
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assign ssel_dec[2] = (m0_adr_i[aw -1 : aw - decode_w ] == s2_addr);
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assign ssel_dec[3] = (m0_adr_i[aw -1 : aw - decode_w ] == s3_addr);
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assign ssel_dec[4] = (m0_adr_i[aw -1 : aw - decode_w ] == s4_addr);
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assign ssel_dec[5] = (m0_adr_i[aw -1 : aw - decode_w ] == s5_addr);
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assign ssel_dec[6] = (m0_adr_i[aw -1 : aw - decode_w ] == s6_addr);
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assign ssel_dec[7] = (m0_adr_i[aw -1 : aw - decode_w ] == s7_addr);
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assign ssel_dec[8] = (m0_adr_i[aw -1 : aw - decode_w ] == s8_addr);
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assign ssel_dec[9] = (m0_adr_i[aw -1 : aw - decode_w ] == s9_addr);
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assign ssel_dec[10] = (m0_adr_i[aw -1 : aw - decode_w ] == sa_addr);
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assign ssel_dec[11] = (m0_adr_i[aw -1 : aw - decode_w ] == sb_addr);
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assign ssel_dec[12] = (m0_adr_i[aw -1 : aw - decode_w ] == sc_addr);
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assign ssel_dec[13] = (m0_adr_i[aw -1 : aw - decode_w ] == sd_addr);
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assign ssel_dec[14] = (m0_adr_i[aw -1 : aw - decode_w ] == se_addr);
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assign ssel_dec[15] = (m0_adr_i[aw -1 : aw - decode_w ] == sf_addr);
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*/
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endmodule // wb_1master
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