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51 lines
1.4 KiB
Verilog
51 lines
1.4 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module wb_ram_dist
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#(parameter AWIDTH=8)
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(input clk_i,
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input stb_i,
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input we_i,
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input [AWIDTH-1:0] adr_i,
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input [31:0] dat_i,
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input [3:0] sel_i,
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output [31:0] dat_o,
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output ack_o);
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reg [31:0] distram [0:1<<(AWIDTH-1)];
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always @(posedge clk_i)
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begin
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if(stb_i & we_i & sel_i[3])
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distram[adr_i][31:24] <= dat_i[31:24];
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if(stb_i & we_i & sel_i[2])
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distram[adr_i][24:16] <= dat_i[24:16];
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if(stb_i & we_i & sel_i[1])
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distram[adr_i][15:8] <= dat_i[15:8];
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if(stb_i & we_i & sel_i[0])
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distram[adr_i][7:0] <= dat_i[7:0];
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end // always @ (posedge clk_i)
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assign dat_o = distram[adr_i];
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assign ack_o = stb_i;
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endmodule // wb_ram_dist
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