mirror of
https://github.com/fairwaves/UHD-Fairwaves.git
synced 2025-11-03 05:23:14 +00:00
131 lines
3.6 KiB
Plaintext
131 lines
3.6 KiB
Plaintext
##############################################################
|
|
#
|
|
# Xilinx Core Generator version 12.1
|
|
# Date: Wed Jul 21 18:51:14 2010
|
|
#
|
|
##############################################################
|
|
#
|
|
# This file contains the customisation parameters for a
|
|
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
|
# that you do not manually alter this file as it may cause
|
|
# unexpected and unsupported behavior.
|
|
#
|
|
##############################################################
|
|
#
|
|
# BEGIN Project Options
|
|
SET addpads = false
|
|
SET asysymbol = true
|
|
SET busformat = BusFormatAngleBracketNotRipped
|
|
SET createndf = false
|
|
SET designentry = Verilog
|
|
SET device = xc3s2000
|
|
SET devicefamily = spartan3
|
|
SET flowvendor = Other
|
|
SET formalverification = false
|
|
SET foundationsym = false
|
|
SET implementationfiletype = Ngc
|
|
SET package = fg456
|
|
SET removerpms = false
|
|
SET simulationfiles = Structural
|
|
SET speedgrade = -5
|
|
SET verilogsim = true
|
|
SET vhdlsim = false
|
|
# END Project Options
|
|
# BEGIN Select
|
|
SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.03.a
|
|
# END Select
|
|
# BEGIN Parameters
|
|
CSET component_name=ila
|
|
CSET counter_width_1=Disabled
|
|
CSET counter_width_10=Disabled
|
|
CSET counter_width_11=Disabled
|
|
CSET counter_width_12=Disabled
|
|
CSET counter_width_13=Disabled
|
|
CSET counter_width_14=Disabled
|
|
CSET counter_width_15=Disabled
|
|
CSET counter_width_16=Disabled
|
|
CSET counter_width_2=Disabled
|
|
CSET counter_width_3=Disabled
|
|
CSET counter_width_4=Disabled
|
|
CSET counter_width_5=Disabled
|
|
CSET counter_width_6=Disabled
|
|
CSET counter_width_7=Disabled
|
|
CSET counter_width_8=Disabled
|
|
CSET counter_width_9=Disabled
|
|
CSET data_port_width=0
|
|
CSET data_same_as_trigger=true
|
|
CSET enable_storage_qualification=true
|
|
CSET enable_trigger_output_port=false
|
|
CSET exclude_from_data_storage_1=false
|
|
CSET exclude_from_data_storage_10=false
|
|
CSET exclude_from_data_storage_11=false
|
|
CSET exclude_from_data_storage_12=false
|
|
CSET exclude_from_data_storage_13=false
|
|
CSET exclude_from_data_storage_14=false
|
|
CSET exclude_from_data_storage_15=false
|
|
CSET exclude_from_data_storage_16=false
|
|
CSET exclude_from_data_storage_2=false
|
|
CSET exclude_from_data_storage_3=false
|
|
CSET exclude_from_data_storage_4=false
|
|
CSET exclude_from_data_storage_5=false
|
|
CSET exclude_from_data_storage_6=false
|
|
CSET exclude_from_data_storage_7=false
|
|
CSET exclude_from_data_storage_8=false
|
|
CSET exclude_from_data_storage_9=false
|
|
CSET match_type_1=basic
|
|
CSET match_type_10=basic
|
|
CSET match_type_11=basic
|
|
CSET match_type_12=basic
|
|
CSET match_type_13=basic
|
|
CSET match_type_14=basic
|
|
CSET match_type_15=basic
|
|
CSET match_type_16=basic
|
|
CSET match_type_2=basic
|
|
CSET match_type_3=basic
|
|
CSET match_type_4=basic
|
|
CSET match_type_5=basic
|
|
CSET match_type_6=basic
|
|
CSET match_type_7=basic
|
|
CSET match_type_8=basic
|
|
CSET match_type_9=basic
|
|
CSET match_units_1=1
|
|
CSET match_units_10=1
|
|
CSET match_units_11=1
|
|
CSET match_units_12=1
|
|
CSET match_units_13=1
|
|
CSET match_units_14=1
|
|
CSET match_units_15=1
|
|
CSET match_units_16=1
|
|
CSET match_units_2=1
|
|
CSET match_units_3=1
|
|
CSET match_units_4=1
|
|
CSET match_units_5=1
|
|
CSET match_units_6=1
|
|
CSET match_units_7=1
|
|
CSET match_units_8=1
|
|
CSET match_units_9=1
|
|
CSET max_sequence_levels=1
|
|
CSET number_of_trigger_ports=4
|
|
CSET sample_data_depth=512
|
|
CSET sample_on=Rising
|
|
CSET trigger_port_width_1=8
|
|
CSET trigger_port_width_10=8
|
|
CSET trigger_port_width_11=8
|
|
CSET trigger_port_width_12=8
|
|
CSET trigger_port_width_13=8
|
|
CSET trigger_port_width_14=8
|
|
CSET trigger_port_width_15=8
|
|
CSET trigger_port_width_16=8
|
|
CSET trigger_port_width_2=8
|
|
CSET trigger_port_width_3=8
|
|
CSET trigger_port_width_4=4
|
|
CSET trigger_port_width_5=8
|
|
CSET trigger_port_width_6=8
|
|
CSET trigger_port_width_7=8
|
|
CSET trigger_port_width_8=8
|
|
CSET trigger_port_width_9=8
|
|
CSET use_rpms=true
|
|
# END Parameters
|
|
GENERATE
|
|
# CRC: 66151c7c
|