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128 lines
3.6 KiB
Verilog
128 lines
3.6 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// Parameter LE tells us if we are little-endian.
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// Little-endian means send lower 16 bits first.
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// Default is big endian (network order), send upper bits first.
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module fifo19_to_fifo36
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#(parameter LE=0)
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(input clk, input reset, input clear,
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input [18:0] f19_datain,
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input f19_src_rdy_i,
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output f19_dst_rdy_o,
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output [35:0] f36_dataout,
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output f36_src_rdy_o,
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input f36_dst_rdy_i,
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output [31:0] debug
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);
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// Shortfifo on input to guarantee no deadlock
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wire [18:0] f19_data_int;
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wire f19_src_rdy_int, f19_dst_rdy_int;
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fifo_short #(.WIDTH(19)) head_fifo
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(.clk(clk),.reset(reset),.clear(clear),
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.datain(f19_datain), .src_rdy_i(f19_src_rdy_i), .dst_rdy_o(f19_dst_rdy_o),
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.dataout(f19_data_int), .src_rdy_o(f19_src_rdy_int), .dst_rdy_i(f19_dst_rdy_int),
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.space(),.occupied() );
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// Actual f19 to f36 which could deadlock if not connected to shortfifos
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reg f36_sof_int, f36_eof_int;
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reg [1:0] f36_occ_int;
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wire [35:0] f36_data_int;
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wire f36_src_rdy_int, f36_dst_rdy_int;
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reg [1:0] state;
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reg [15:0] dat0, dat1;
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wire f19_sof_int = f19_data_int[16];
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wire f19_eof_int = f19_data_int[17];
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wire f19_occ_int = f19_data_int[18];
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wire xfer_out = f36_src_rdy_int & f36_dst_rdy_int;
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always @(posedge clk)
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if(f19_src_rdy_int & ((state==0)|xfer_out))
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f36_sof_int <= f19_sof_int;
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always @(posedge clk)
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if(f19_src_rdy_int & ((state != 2)|xfer_out))
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f36_eof_int <= f19_eof_int;
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always @(posedge clk)
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if(reset)
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begin
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state <= 0;
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f36_occ_int <= 0;
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end
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else
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if(f19_src_rdy_int)
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case(state)
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0 :
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begin
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dat0 <= f19_data_int;
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if(f19_eof_int)
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begin
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state <= 2;
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f36_occ_int <= f19_occ_int ? 2'b01 : 2'b10;
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end
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else
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state <= 1;
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end
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1 :
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begin
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dat1 <= f19_data_int;
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state <= 2;
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if(f19_eof_int)
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f36_occ_int <= f19_occ_int ? 2'b11 : 2'b00;
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end
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2 :
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if(xfer_out)
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begin
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dat0 <= f19_data_int;
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if(f19_eof_int) // remain in state 2 if we are at eof
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f36_occ_int <= f19_occ_int ? 2'b01 : 2'b10;
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else
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state <= 1;
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end
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endcase // case(state)
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else
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if(xfer_out)
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begin
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state <= 0;
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f36_occ_int <= 0;
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end
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assign f19_dst_rdy_int = xfer_out | (state != 2);
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assign f36_data_int = LE ? {f36_occ_int,f36_eof_int,f36_sof_int,dat1,dat0} :
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{f36_occ_int,f36_eof_int,f36_sof_int,dat0,dat1};
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assign f36_src_rdy_int = (state == 2);
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assign debug = state;
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// Shortfifo on output to guarantee no deadlock
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fifo_short #(.WIDTH(36)) tail_fifo
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(.clk(clk),.reset(reset),.clear(clear),
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.datain(f36_data_int), .src_rdy_i(f36_src_rdy_int), .dst_rdy_o(f36_dst_rdy_int),
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.dataout(f36_dataout), .src_rdy_o(f36_src_rdy_o), .dst_rdy_i(f36_dst_rdy_i),
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.space(),.occupied() );
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endmodule // fifo19_to_fifo36
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