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113 lines
2.6 KiB
Verilog
113 lines
2.6 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module fifo_short
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#(parameter WIDTH=32)
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(input clk, input reset, input clear,
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input [WIDTH-1:0] datain,
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input src_rdy_i,
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output dst_rdy_o,
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output [WIDTH-1:0] dataout,
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output src_rdy_o,
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input dst_rdy_i,
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output reg [4:0] space,
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output reg [4:0] occupied);
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reg full, empty;
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wire write = src_rdy_i & dst_rdy_o;
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wire read = dst_rdy_i & src_rdy_o;
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assign dst_rdy_o = ~full;
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assign src_rdy_o = ~empty;
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reg [3:0] a;
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genvar i;
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generate
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for (i=0;i<WIDTH;i=i+1)
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begin : gen_srl16
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SRL16E
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srl16e(.Q(dataout[i]),
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.A0(a[0]),.A1(a[1]),.A2(a[2]),.A3(a[3]),
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.CE(write),.CLK(clk),.D(datain[i]));
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end
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endgenerate
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always @(posedge clk)
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if(reset)
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begin
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a <= 0;
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empty <= 1;
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full <= 0;
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end
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else if(clear)
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begin
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a <= 0;
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empty <= 1;
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full<= 0;
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end
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else if(read & ~write)
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begin
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full <= 0;
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if(a==0)
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empty <= 1;
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else
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a <= a - 1;
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end
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else if(write & ~read)
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begin
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empty <= 0;
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if(~empty)
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a <= a + 1;
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if(a == 14)
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full <= 1;
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end
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// NOTE will fail if you write into a full fifo or read from an empty one
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//////////////////////////////////////////////////////////////
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// space and occupied are used for diagnostics, not
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// guaranteed correct
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//assign space = full ? 0 : empty ? 16 : 15-a;
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//assign occupied = empty ? 0 : full ? 16 : a+1;
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always @(posedge clk)
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if(reset)
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space <= 16;
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else if(clear)
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space <= 16;
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else if(read & ~write)
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space <= space + 1;
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else if(write & ~read)
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space <= space - 1;
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always @(posedge clk)
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if(reset)
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occupied <= 0;
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else if(clear)
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occupied <= 0;
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else if(read & ~write)
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occupied <= occupied - 1;
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else if(write & ~read)
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occupied <= occupied + 1;
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endmodule // fifo_short
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