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34 lines
1.0 KiB
Verilog
34 lines
1.0 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module mult (input clock, input signed [15:0] x, input signed [15:0] y, output reg signed [30:0] product,
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input enable_in, output reg enable_out );
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always @(posedge clock)
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if(enable_in)
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product <= #1 x*y;
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else
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product <= #1 31'd0;
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always @(posedge clock)
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enable_out <= #1 enable_in;
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endmodule // mult
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