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60 lines
2.1 KiB
Verilog
60 lines
2.1 KiB
Verilog
// -*- verilog -*-
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//
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// USRP - Universal Software Radio Peripheral
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//
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// Copyright (C) 2011 Matt Ettus
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
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//
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// Rounding "macro"
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// Keeps the topmost bits, does proper 2s comp round to zero (unbiased truncation)
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module round
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#(parameter bits_in=0,
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parameter bits_out=0,
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parameter round_to_zero=0, // original behavior
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parameter round_to_nearest=1, // lowest noise
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parameter trunc=0) // round to negative infinity
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(input [bits_in-1:0] in,
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output [bits_out-1:0] out,
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output [bits_in-bits_out:0] err);
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wire round_corr,round_corr_trunc,round_corr_rtz,round_corr_nearest,round_corr_nearest_safe;
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assign round_corr_trunc = 0;
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assign round_corr_rtz = (in[bits_in-1] & |in[bits_in-bits_out-1:0]);
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assign round_corr_nearest = in[bits_in-bits_out-1];
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generate
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if(bits_in-bits_out > 1)
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assign round_corr_nearest_safe = (~in[bits_in-1] & (&in[bits_in-2:bits_out])) ? 0 :
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round_corr_nearest;
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else
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assign round_corr_nearest_safe = round_corr_nearest;
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endgenerate
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assign round_corr = round_to_nearest ? round_corr_nearest_safe :
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trunc ? round_corr_trunc :
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round_to_zero ? round_corr_rtz :
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0; // default to trunc
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assign out = in[bits_in-1:bits_in-bits_out] + round_corr;
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assign err = in - {out,{(bits_in-bits_out){1'b0}}};
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endmodule // round
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