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59 lines
1.9 KiB
Verilog
59 lines
1.9 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module rx_dcoffset
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#(parameter WIDTH=16,
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parameter ADDR=8'd0,
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parameter alpha_shift=20)
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(input clk, input rst,
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input set_stb, input [7:0] set_addr, input [31:0] set_data,
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input [WIDTH-1:0] in, output [WIDTH-1:0] out);
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wire set_now = set_stb & (ADDR == set_addr);
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reg fixed; // uses fixed offset
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wire [WIDTH-1:0] fixed_dco;
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localparam int_width = WIDTH + alpha_shift;
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reg [int_width-1:0] integrator;
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wire [WIDTH-1:0] quantized;
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always @(posedge clk)
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if(rst)
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begin
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fixed <= 0;
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integrator <= {int_width{1'b0}};
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end
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else if(set_now)
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begin
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fixed <= set_data[31];
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if(set_data[30])
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integrator <= {set_data[29:0],{(int_width-30){1'b0}}};
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end
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else if(~fixed)
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integrator <= integrator + {{(alpha_shift){out[WIDTH-1]}},out};
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round_sd #(.WIDTH_IN(int_width),.WIDTH_OUT(WIDTH)) round_sd
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(.clk(clk), .reset(rst), .in(integrator), .strobe_in(1'b1), .out(quantized), .strobe_out());
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add2_and_clip_reg #(.WIDTH(WIDTH)) add2_and_clip_reg
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(.clk(clk), .rst(rst), .in1(in), .in2(-quantized), .strobe_in(1'b1), .sum(out), .strobe_out());
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endmodule // rx_dcoffset
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