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https://github.com/fairwaves/UHD-Fairwaves.git
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55 lines
1.4 KiB
Verilog
55 lines
1.4 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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`timescale 1ns/1ns
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module rx_dcoffset_tb();
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reg clk, rst;
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initial rst = 1;
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initial #1000 rst = 0;
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initial clk = 0;
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always #5 clk = ~clk;
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initial $dumpfile("rx_dcoffset_tb.vcd");
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initial $dumpvars(0,rx_dcoffset_tb);
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reg [13:0] adc_in;
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wire [13:0] adc_out;
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always @(posedge clk)
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begin
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if(adc_in[13])
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$write("-%d,",-adc_in);
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else
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$write("%d,",adc_in);
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if(adc_out[13])
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$write("-%d\n",-adc_out);
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else
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$write("%d\n",adc_out);
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end
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rx_dcoffset #(.WIDTH(14),.ADDR(0), .alpha_shift(8))
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rx_dcoffset(.clk(clk),.rst(rst),.set_stb(0),.set_addr(0),.set_data(0),
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.in(adc_in),.out(adc_out));
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always @(posedge clk)
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adc_in <= (($random % 473) + 23)/4;
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endmodule // longfifo_tb
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