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80 lines
1.9 KiB
Verilog
80 lines
1.9 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module serdes_fc_rx
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#(parameter LWMARK = 64,
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parameter HWMARK = 320)
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(input clk, input rst,
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input [15:0] fifo_space,
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output reg send_xon,
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output reg send_xoff,
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input sent);
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reg [15:0] countdown;
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reg send_xon_int, send_xoff_int;
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always @(posedge clk)
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if(rst)
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begin
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send_xon_int <= 0;
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send_xoff_int <= 0;
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countdown <= 0;
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end
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else
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begin
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send_xon_int <= 0;
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send_xoff_int <= 0;
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if(countdown == 0)
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if(fifo_space < LWMARK)
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begin
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send_xoff_int <= 1;
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countdown <= 240;
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end
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else
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;
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else
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if(fifo_space > HWMARK)
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begin
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send_xon_int <= 1;
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countdown <= 0;
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end
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else
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countdown <= countdown - 1;
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end // else: !if(rst)
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// If we are between the high and low water marks, we let the countdown expire
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always @(posedge clk)
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if(rst)
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send_xon <= 0;
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else if(send_xon_int)
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send_xon <= 1;
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else if(sent)
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send_xon <= 0;
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always @(posedge clk)
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if(rst)
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send_xoff <= 0;
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else if(send_xoff_int)
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send_xoff <= 1;
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else if(sent)
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send_xoff <= 0;
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endmodule // serdes_fc_rx
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