mirror of
https://github.com/fairwaves/UHD-Fairwaves.git
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136 lines
4.7 KiB
C++
136 lines
4.7 KiB
C++
//
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// Copyright 2010-2011 Ettus Research LLC
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// Copyright 2012 Fairwaves
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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#ifndef INCLUDED_UMTRX_REGS_HPP
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#define INCLUDED_UMTRX_REGS_HPP
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#define localparam static const int
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////////////////////////////////////////////////////////////////////////
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// Define slave bases
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////////////////////////////////////////////////////////////////////////
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#define ROUTER_RAM_BASE 0x4000
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#define SPI_BASE 0x5000
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#define I2C_BASE 0x5400
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#define GPIO_BASE 0x5800
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#define READBACK_BASE 0x5C00
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#define ETH_BASE 0x6000
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#define SETTING_REGS_BASE 0x7000
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#define PIC_BASE 0x8000
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#define I2C_AUX_BASE 0x8400
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#define UART_BASE 0x8800
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#define ATR_BASE 0x8C00
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////////////////////////////////////////////////////////////////////////
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// Setting register offsets
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////////////////////////////////////////////////////////////////////////
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localparam SR_MISC = 0; // 9 regs
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localparam SR_TIME64 = 10; // 6
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localparam SR_BUF_POOL = 16; // 4
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localparam SR_RX_FRONT0 = 20; // 5
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localparam SR_RX_FRONT1 = 25; // 5
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localparam SR_RX_CTRL0 = 30; // 9
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localparam SR_RX_DSP0 = 40; // 7
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localparam SR_RX_CTRL1 = 50; // 9
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localparam SR_RX_DSP1 = 60; // 7
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localparam SR_RX_CTRL2 = 70; // 9
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localparam SR_RX_DSP2 = 80; // 7
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localparam SR_RX_CTRL3 = 90; // 9
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localparam SR_RX_DSP3 = 100; // 7
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localparam SR_TX_FRONT0 = 110; // ?
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localparam SR_TX_CTRL0 = 126; // 6
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localparam SR_TX_DSP0 = 135; // 5
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localparam SR_TX_FRONT1 = 145; // ?
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localparam SR_TX_CTRL1 = 161; // 6
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localparam SR_TX_DSP1 = 170; // 5
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localparam SR_DIVSW = 180; // 2
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localparam SR_RX_FE_SW = 183; // 1
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localparam SR_TX_FE_SW = 184; // 1
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localparam SR_SPI_CORE = 185; // 3
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#define U2_REG_SR_ADDR(sr) (SETTING_REGS_BASE + (4 * (sr)))
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/////////////////////////////////////////////////
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// SPI Slave Constants
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////////////////////////////////////////////////
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// Masks for controlling different peripherals in UmTRX
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#define SPI_SS_LMS1 1
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#define SPI_SS_LMS2 2
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#define SPI_SS_DAC 4
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#define SPI_SS_AUX1 8
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#define SPI_SS_AUX2 16
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/////////////////////////////////////////////////
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// Misc Control
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////////////////////////////////////////////////
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#define U2_REG_MISC_LMS_RES U2_REG_SR_ADDR(0)
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#define U2_REG_MISC_CTRL_SFC_CLEAR U2_REG_SR_ADDR(1)
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#define U2_REG_MISC_CTRL_LEDS U2_REG_SR_ADDR(3)
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#define U2_REG_MISC_CTRL_PHY U2_REG_SR_ADDR(4)
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#define U2_REG_MISC_CTRL_DBG_MUX U2_REG_SR_ADDR(5)
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#define U2_REG_MISC_CTRL_RAM_PAGE U2_REG_SR_ADDR(6)
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#define U2_REG_MISC_CTRL_FLUSH_ICACHE U2_REG_SR_ADDR(7)
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/////////////////////////////////////////////////
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// Readback regs
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////////////////////////////////////////////////
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#define U2_REG_SPI_RB READBACK_BASE + 4*0
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#define U2_REG_NUM_DDC READBACK_BASE + 4*1
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#define U2_REG_NUM_DUC READBACK_BASE + 4*2
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#define U2_REG_STATUS READBACK_BASE + 4*8
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#define U2_REG_TIME64_HI_RB_IMM READBACK_BASE + 4*10
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#define U2_REG_TIME64_LO_RB_IMM READBACK_BASE + 4*11
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#define U2_REG_COMPAT_NUM_RB READBACK_BASE + 4*12
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#define U2_REG_IRQ_RB READBACK_BASE + 4*13
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#define U2_REG_TIME64_HI_RB_PPS READBACK_BASE + 4*14
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#define U2_REG_TIME64_LO_RB_PPS READBACK_BASE + 4*15
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#define AUX_LD1_IRQ_BIT (1 << 14)
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#define AUX_LD2_IRQ_BIT (1 << 15)
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/////////////////////////////////////////////////
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// LMS regs
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////////////////////////////////////////////////
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#define LMS_BITS(val, shift, mask) (((val)<<(shift))&(mask))
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#define LMS_DC_CAL_REG 0x33
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#define LMS_DC_START_CLBR_SHIFT 5
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#define LMS_DC_START_CLBR_MASK (1<<LMS_DC_START_CLBR_SHIFT)
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#define LMS_DC_LOAD_SHIFT 4
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#define LMS_DC_LOAD_MASK (1<<LMS_DC_LOAD_SHIFT)
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#define LMS_DC_SRESET_SHIFT 3
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#define LMS_DC_SRESET_MASK (1<<LMS_DC_SRESET_SHIFT)
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#define LMS_DC_ADDR_SHIFT 0
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#define LMS_DC_ADDR_MASK (7<<LMS_DC_ADDR_SHIFT)
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// Defined for the U2_REG_MISC_LMS_CLOCK register
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#define LMS1_RESET (1<<0)
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#define LMS2_RESET (1<<1)
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// Defined for the U2_REG_MISC_LMS_RES register
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#define PAREG_NLOW_PA (1<<2)
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#define PAREG_ENPA1 (1<<3)
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#define PAREG_ENPA2 (1<<4)
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#define PAREG_ENDCSYNC (1<<5)
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#endif
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