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https://github.com/fairwaves/UHD-Fairwaves.git
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93 lines
3.0 KiB
Verilog
93 lines
3.0 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module fifo36_to_ll8
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(input clk, input reset, input clear,
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input [35:0] f36_data,
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input f36_src_rdy_i,
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output f36_dst_rdy_o,
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output [7:0] ll_data,
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output ll_sof,
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output ll_eof,
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output ll_src_rdy,
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input ll_dst_rdy,
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output [31:0] debug);
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// Shortfifo on input to guarantee no deadlock
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wire [35:0] f36_data_int;
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wire f36_src_rdy_int, f36_dst_rdy_int;
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reg [7:0] ll_data_int;
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wire ll_sof_int, ll_eof_int, ll_src_rdy_int, ll_dst_rdy_int;
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fifo_short #(.WIDTH(36)) head_fifo
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(.clk(clk),.reset(reset),.clear(clear),
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.datain(f36_data), .src_rdy_i(f36_src_rdy_i), .dst_rdy_o(f36_dst_rdy_o),
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.dataout(f36_data_int), .src_rdy_o(f36_src_rdy_int), .dst_rdy_i(f36_dst_rdy_int),
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.space(),.occupied() );
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// Actual fifo36 to ll8, can deadlock if not connected to shortfifo
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wire [1:0] f36_occ_int = f36_data_int[35:34];
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wire f36_sof_int = f36_data_int[32];
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wire f36_eof_int = f36_data_int[33];
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wire advance, end_early;
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reg [1:0] state;
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assign debug = {29'b0,state};
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always @(posedge clk)
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if(reset)
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state <= 0;
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else
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if(advance)
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if(ll_eof_int)
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state <= 0;
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else
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state <= state + 1;
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always @*
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case(state)
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0 : ll_data_int = f36_data_int[31:24];
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1 : ll_data_int = f36_data_int[23:16];
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2 : ll_data_int = f36_data_int[15:8];
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3 : ll_data_int = f36_data_int[7:0];
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default : ll_data_int = f36_data_int[31:24];
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endcase // case (state)
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assign ll_sof_int = (state==0) & f36_sof_int;
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assign ll_eof_int = f36_eof_int & (((state==0)&(f36_occ_int==1)) |
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((state==1)&(f36_occ_int==2)) |
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((state==2)&(f36_occ_int==3)) |
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(state==3));
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assign ll_src_rdy_int = f36_src_rdy_int;
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assign advance = ll_src_rdy_int & ll_dst_rdy_int;
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assign f36_dst_rdy_int= advance & ((state==3)|ll_eof_int);
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// Short FIFO on output to guarantee no deadlock
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ll8_shortfifo tail_fifo
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(.clk(clk), .reset(reset), .clear(clear),
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.datain(ll_data_int), .sof_i(ll_sof_int), .eof_i(ll_eof_int),
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.error_i(0), .src_rdy_i(ll_src_rdy_int), .dst_rdy_o(ll_dst_rdy_int),
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.dataout(ll_data), .sof_o(ll_sof), .eof_o(ll_eof),
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.error_o(), .src_rdy_o(ll_src_rdy), .dst_rdy_i(ll_dst_rdy));
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endmodule // fifo36_to_ll8
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