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47 lines
1.4 KiB
Verilog
47 lines
1.4 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module valve36
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(input clk, input reset, input clear,
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input shutoff,
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input [35:0] data_i, input src_rdy_i, output dst_rdy_o,
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output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
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reg shutoff_int, active;
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wire active_next = (src_rdy_i & dst_rdy_o)? ~data_i[33] : active;
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assign data_o = data_i;
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assign dst_rdy_o = shutoff_int ? 1'b1 : dst_rdy_i;
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assign src_rdy_o = shutoff_int ? 1'b0 : src_rdy_i;
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always @(posedge clk)
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if(reset | clear)
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active <= 0;
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else
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active <= active_next;
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always @(posedge clk)
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if(reset | clear)
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shutoff_int <= 0;
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else if(~active_next)
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shutoff_int <= shutoff;
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endmodule // valve36
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