mirror of
https://github.com/fairwaves/UHD-Fairwaves.git
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85 lines
2.4 KiB
Verilog
85 lines
2.4 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// Dual ported, Harvard architecture, cached ram
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module ram_harvard
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#(parameter AWIDTH=15,
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parameter RAM_SIZE=16384,
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parameter ICWIDTH=6,
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parameter DCWIDTH=6)
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(input wb_clk_i,
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input wb_rst_i,
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// Firmware download port.
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input [AWIDTH-1:0] ram_loader_adr_i,
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input [31:0] ram_loader_dat_i,
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input [3:0] ram_loader_sel_i,
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input ram_loader_stb_i,
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input ram_loader_we_i,
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input ram_loader_done_i,
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// Instruction fetch port.
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input [AWIDTH-1:0] if_adr,
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output [31:0] if_data,
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// Data access port.
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input [AWIDTH-1:0] dwb_adr_i,
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input [31:0] dwb_dat_i,
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output [31:0] dwb_dat_o,
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input dwb_we_i,
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output dwb_ack_o,
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input dwb_stb_i,
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input [3:0] dwb_sel_i );
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reg ack_d1;
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reg stb_d1;
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dpram32 #(.AWIDTH(AWIDTH),.RAM_SIZE(RAM_SIZE))
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sys_ram
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(.clk(wb_clk_i),
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.adr1_i(ram_loader_done_i ? if_adr : ram_loader_adr_i),
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.dat1_i(ram_loader_dat_i),
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.dat1_o(if_data),
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.we1_i(ram_loader_done_i ? 1'b0 : ram_loader_we_i),
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.en1_i(ram_loader_done_i ? 1'b1 : ram_loader_stb_i),
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//.sel1_i(ram_loader_done_i ? 4'hF : ram_loader_sel_i),
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.sel1_i(ram_loader_sel_i), // Sel is only for writes anyway
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.adr2_i(dwb_adr_i),
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.dat2_i(dwb_dat_i),
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.dat2_o(dwb_dat_o),
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.we2_i(dwb_we_i),
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.en2_i(dwb_stb_i),
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.sel2_i(dwb_sel_i)
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);
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assign dwb_ack_o = dwb_stb_i & (dwb_we_i | (stb_d1 & ~ack_d1));
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always @(posedge wb_clk_i)
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if(wb_rst_i)
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ack_d1 <= 1'b0;
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else
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ack_d1 <= dwb_ack_o;
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always @(posedge wb_clk_i)
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if(wb_rst_i)
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stb_d1 <= 0;
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else
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stb_d1 <= dwb_stb_i;
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endmodule // ram_harvard
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