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https://github.com/fairwaves/UHD-Fairwaves.git
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128 lines
4.1 KiB
Verilog
128 lines
4.1 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module prot_eng_tx
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#(parameter BASE=0)
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(input clk, input reset, input clear,
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input set_stb, input [7:0] set_addr, input [31:0] set_data,
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input [35:0] datain, input src_rdy_i, output dst_rdy_o,
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output [35:0] dataout, output src_rdy_o, input dst_rdy_i);
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wire src_rdy_int1, dst_rdy_int1;
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wire src_rdy_int2, dst_rdy_int2;
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wire [35:0] data_int1, data_int2;
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// Shortfifo on input to guarantee no deadlock
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fifo_short #(.WIDTH(36)) head_fifo
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(.clk(clk),.reset(reset),.clear(clear),
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.datain(datain), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
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.dataout(data_int1), .src_rdy_o(src_rdy_int1), .dst_rdy_i(dst_rdy_int1),
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.space(),.occupied() );
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// Store header values in a small dual-port (distributed) ram
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reg [31:0] header_ram[0:127];
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reg [3:0] state;
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reg [2:0] port_sel;
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always @(posedge clk)
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if(set_stb & ((set_addr & 8'h80) == BASE))
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header_ram[set_addr[6:0]] <= set_data;
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wire [31:0] header_word = header_ram[{port_sel[2:0],state[3:0]}];
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reg [15:0] pre_checksums [0:7];
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always @(posedge clk)
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if(set_stb & ((set_addr & 8'h8F)== (BASE+7)))
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pre_checksums[set_addr[6:4]] <= set_data[15:0];
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wire [15:0] pre_checksum = pre_checksums[port_sel[2:0]];
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// Protocol State Machine
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reg [15:0] length;
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wire [15:0] ip_length = length + 28; // IP HDR + UDP HDR
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wire [15:0] udp_length = length + 8; // UDP HDR
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reg sof_o;
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reg [31:0] prot_data;
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always @(posedge clk)
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if(reset)
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begin
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state <= 0;
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sof_o <= 0;
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end
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else
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if(src_rdy_int1 & dst_rdy_int2)
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case(state)
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0 :
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begin
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port_sel <= data_int1[19:17];
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length <= data_int1[15:0];
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sof_o <= 1;
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if(data_int1[16])
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state <= 1;
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else
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state <= 12;
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end
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12 :
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begin
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sof_o <= 0;
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if(data_int1[33]) // eof
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state <= 0;
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end
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default :
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begin
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sof_o <= 0;
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state <= state + 1;
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end
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endcase // case (state)
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wire [15:0] ip_checksum;
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add_onescomp #(.WIDTH(16)) add_onescomp
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(.A(pre_checksum),.B(ip_length),.SUM(ip_checksum));
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reg [15:0] ip_checksum_reg;
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always @(posedge clk) ip_checksum_reg <= ip_checksum;
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always @*
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case(state)
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1 : prot_data <= header_word; // ETH, top half ignored
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2 : prot_data <= header_word; // ETH
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3 : prot_data <= header_word; // ETH
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4 : prot_data <= header_word; // ETH
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5 : prot_data <= { header_word[31:16], ip_length }; // IP
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6 : prot_data <= header_word; // IP
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7 : prot_data <= { header_word[31:16], (16'hFFFF ^ ip_checksum_reg) }; // IP
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8 : prot_data <= header_word; // IP
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9 : prot_data <= header_word; // IP
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10: prot_data <= header_word; // UDP
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11: prot_data <= { udp_length, header_word[15:0]}; // UDP
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default : prot_data <= data_int1[31:0];
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endcase // case (state)
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assign data_int2 = { data_int1[35:33] & {3{state[3]}}, sof_o, prot_data };
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assign dst_rdy_int1 = dst_rdy_int2 & ((state == 0) | (state == 12));
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assign src_rdy_int2 = src_rdy_int1 & (state != 0);
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// Shortfifo on output to guarantee no deadlock
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fifo_short #(.WIDTH(36)) tail_fifo
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(.clk(clk),.reset(reset),.clear(clear),
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.datain(data_int2), .src_rdy_i(src_rdy_int2), .dst_rdy_o(dst_rdy_int2),
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.dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i),
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.space(),.occupied() );
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endmodule // prot_eng_tx
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