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https://github.com/fairwaves/UHD-Fairwaves.git
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72 lines
2.2 KiB
Verilog
72 lines
2.2 KiB
Verilog
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//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module gpio_atr
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#(parameter BASE = 0,
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parameter WIDTH = 32)
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(input clk, input reset,
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input set_stb, input [7:0] set_addr, input [31:0] set_data,
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input rx, input tx,
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inout [WIDTH-1:0] gpio,
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output reg [31:0] gpio_readback
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);
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wire [WIDTH-1:0] ddr, in_idle, in_tx, in_rx, in_fdx;
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reg [WIDTH-1:0] rgpio, igpio;
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setting_reg #(.my_addr(BASE+0), .width(WIDTH)) reg_idle
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(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),
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.out(in_idle),.changed());
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setting_reg #(.my_addr(BASE+1), .width(WIDTH)) reg_rx
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(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),
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.out(in_rx),.changed());
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setting_reg #(.my_addr(BASE+2), .width(WIDTH)) reg_tx
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(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),
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.out(in_tx),.changed());
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setting_reg #(.my_addr(BASE+3), .width(WIDTH)) reg_fdx
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(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),
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.out(in_fdx),.changed());
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setting_reg #(.my_addr(BASE+4), .width(WIDTH)) reg_ddr
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(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),
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.out(ddr),.changed());
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always @(posedge clk)
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case({tx,rx})
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2'b00: rgpio <= in_idle;
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2'b01: rgpio <= in_rx;
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2'b10: rgpio <= in_tx;
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2'b11: rgpio <= in_fdx;
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endcase // case ({tx,rx})
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integer n;
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always @*
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for(n=0;n<WIDTH;n=n+1)
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igpio[n] <= ddr[n] ? rgpio[n] : 1'bz;
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assign gpio = igpio;
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always @(posedge clk)
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gpio_readback <= gpio;
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endmodule // gpio_atr
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