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39 lines
1.2 KiB
Verilog
39 lines
1.2 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module mux8
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#(parameter WIDTH=32, parameter DISABLED=0)
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(input en,
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input [2:0] sel,
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input [WIDTH-1:0] i0,
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input [WIDTH-1:0] i1,
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input [WIDTH-1:0] i2,
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input [WIDTH-1:0] i3,
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input [WIDTH-1:0] i4,
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input [WIDTH-1:0] i5,
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input [WIDTH-1:0] i6,
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input [WIDTH-1:0] i7,
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output [WIDTH-1:0] o);
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assign o = en ? (sel[2] ? (sel[1] ? (sel[0] ? i7 : i6) : (sel[0] ? i5 : i4)) :
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(sel[1] ? (sel[0] ? i3 : i2) : (sel[0] ? i1 : i0))) :
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DISABLED;
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endmodule // mux8
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