mirror of
https://github.com/fairwaves/UHD-Fairwaves.git
synced 2025-11-03 21:43:15 +00:00
88 lines
2.2 KiB
Verilog
88 lines
2.2 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module sd_spi
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(input clk,
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input rst,
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// SD Card interface
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output reg sd_clk,
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output sd_mosi,
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input sd_miso,
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// Controls
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input [7:0] clk_div,
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input [7:0] send_dat,
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output [7:0] rcv_dat,
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input go,
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output ready);
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reg [7:0] clk_ctr;
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reg [3:0] bit_ctr;
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wire bit_ready = (clk_ctr == 8'd0);
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wire bit_busy = (clk_ctr != 8'd0);
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wire bit_done = (clk_ctr == clk_div);
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wire send_clk_hi = (clk_ctr == (clk_div>>1));
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wire latch_dat = (clk_ctr == (clk_div - 8'd2));
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wire send_clk_lo = (clk_ctr == (clk_div - 8'd1));
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wire send_bit = (bit_ready && (bit_ctr != 0));
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assign ready = (bit_ctr == 0);
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always @(posedge clk)
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if(rst)
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clk_ctr <= 0;
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else if(bit_done)
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clk_ctr <= 0;
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else if(bit_busy)
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clk_ctr <= clk_ctr + 1;
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else if(send_bit)
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clk_ctr <= 1;
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always @(posedge clk)
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if(rst)
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sd_clk <= 0;
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else if(send_clk_hi)
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sd_clk <= 1;
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else if(send_clk_lo)
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sd_clk <= 0;
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always @(posedge clk)
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if(rst)
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bit_ctr <= 0;
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else if(bit_done)
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if(bit_ctr == 4'd8)
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bit_ctr <= 0;
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else
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bit_ctr <= bit_ctr + 1;
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else if(bit_ready & go)
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bit_ctr <= 1;
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reg [7:0] shift_reg;
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always @(posedge clk)
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if(go)
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shift_reg <= send_dat;
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else if(latch_dat)
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shift_reg <= {shift_reg[6:0],sd_miso};
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assign sd_mosi = shift_reg[7];
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assign rcv_dat = shift_reg;
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endmodule // sd_spi
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