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78 lines
2.1 KiB
Verilog
78 lines
2.1 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// Note -- clocks must be synchronous (derived from the same source)
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// Assumes alt_clk is running at a multiple of wb_clk
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module wb_readback_mux
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(input wb_clk_i,
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input wb_rst_i,
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input wb_stb_i,
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input [15:0] wb_adr_i,
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output reg [31:0] wb_dat_o,
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output reg wb_ack_o,
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input [31:0] word00,
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input [31:0] word01,
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input [31:0] word02,
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input [31:0] word03,
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input [31:0] word04,
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input [31:0] word05,
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input [31:0] word06,
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input [31:0] word07,
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input [31:0] word08,
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input [31:0] word09,
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input [31:0] word10,
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input [31:0] word11,
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input [31:0] word12,
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input [31:0] word13,
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input [31:0] word14,
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input [31:0] word15
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);
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always @(posedge wb_clk_i)
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if(wb_rst_i)
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wb_ack_o <= 0;
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else
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wb_ack_o <= wb_stb_i & ~wb_ack_o;
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always @(posedge wb_clk_i)
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case(wb_adr_i[5:2])
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0 : wb_dat_o <= word00;
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1 : wb_dat_o <= word01;
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2 : wb_dat_o <= word02;
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3 : wb_dat_o <= word03;
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4 : wb_dat_o <= word04;
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5 : wb_dat_o <= word05;
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6 : wb_dat_o <= word06;
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7 : wb_dat_o <= word07;
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8 : wb_dat_o <= word08;
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9 : wb_dat_o <= word09;
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10: wb_dat_o <= word10;
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11: wb_dat_o <= word11;
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12: wb_dat_o <= word12;
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13: wb_dat_o <= word13;
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14: wb_dat_o <= word14;
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15: wb_dat_o <= word15;
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endcase // case(addr_reg[3:0])
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endmodule // wb_readback_mux
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