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78 lines
2.7 KiB
Verilog
78 lines
2.7 KiB
Verilog
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// Copyright 2012 Ettus Research LLC
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// axi_demux -- takes one AXI stream, sends to one of 4 output channels
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// Choice of output channel is by external logic based on first line of packet ("header" port)
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// If compressed vita data, this line contains vita header and streamid.
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module axi_demux4
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#(parameter ACTIVE_CHAN = 4'b1111, // ACTIVE_CHAN is a map of connected outputs
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parameter WIDTH = 64,
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parameter BUFFER=0)
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(input clk, input reset, input clear,
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output [WIDTH-1:0] header, input [1:0] dest,
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input [WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
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output [WIDTH-1:0] o0_tdata, output o0_tlast, output o0_tvalid, input o0_tready,
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output [WIDTH-1:0] o1_tdata, output o1_tlast, output o1_tvalid, input o1_tready,
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output [WIDTH-1:0] o2_tdata, output o2_tlast, output o2_tvalid, input o2_tready,
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output [WIDTH-1:0] o3_tdata, output o3_tlast, output o3_tvalid, input o3_tready);
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wire [WIDTH-1:0] i_tdata_int;
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wire i_tlast_int, i_tvalid_int, i_tready_int;
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generate
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if(BUFFER == 0)
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begin
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assign i_tdata_int = i_tdata;
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assign i_tlast_int = i_tlast;
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assign i_tvalid_int = i_tvalid;
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assign i_tready = i_tready_int;
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end
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else
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axi_fifo_short #(.WIDTH(WIDTH+1)) axi_fifo_short
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(.clk(clk), .reset(reset), .clear(clear),
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.i_tdata({i_tlast,i_tdata}), .i_tvalid(i_tvalid), .i_tready(i_tready),
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.o_tdata({i_tlast_int,i_tdata_int}), .o_tvalid(i_tvalid_int), .o_tready(i_tready_int),
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.space(), .occupied());
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endgenerate
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reg [3:0] dm_state;
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localparam DM_IDLE = 4'b0000;
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localparam DM_0 = 4'b0001;
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localparam DM_1 = 4'b0010;
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localparam DM_2 = 4'b0100;
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localparam DM_3 = 4'b1000;
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assign header = i_tdata_int;
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always @(posedge clk)
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if(reset | clear)
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dm_state <= DM_IDLE;
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else
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case (dm_state)
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DM_IDLE :
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if(i_tvalid_int)
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case(dest)
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2'b00 : dm_state <= DM_0;
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2'b01 : dm_state <= DM_1;
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2'b10 : dm_state <= DM_2;
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2'b11 : dm_state <= DM_3;
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endcase // case (i_tdata[1:0])
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DM_0, DM_1, DM_2, DM_3 :
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if(i_tvalid_int & i_tready_int & i_tlast_int)
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dm_state <= DM_IDLE;
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default :
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dm_state <= DM_IDLE;
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endcase // case (dm_state)
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assign {o3_tvalid, o2_tvalid, o1_tvalid, o0_tvalid} = dm_state & {4{i_tvalid_int}};
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assign i_tready_int = |(dm_state & ({o3_tready, o2_tready, o1_tready, o0_tready} | ~ACTIVE_CHAN));
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assign {o0_tlast, o0_tdata} = {i_tlast_int, i_tdata_int};
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assign {o1_tlast, o1_tdata} = {i_tlast_int, i_tdata_int};
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assign {o2_tlast, o2_tdata} = {i_tlast_int, i_tdata_int};
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assign {o3_tlast, o3_tdata} = {i_tlast_int, i_tdata_int};
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endmodule // axi_demux4
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