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39 lines
1.2 KiB
Verilog
39 lines
1.2 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module decoder_3_8
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(input [2:0] sel,
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output reg [7:0] res);
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always @(sel or res)
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begin
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case (sel)
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3'b000 : res = 8'b00000001;
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3'b001 : res = 8'b00000010;
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3'b010 : res = 8'b00000100;
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3'b011 : res = 8'b00001000;
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3'b100 : res = 8'b00010000;
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3'b101 : res = 8'b00100000;
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3'b110 : res = 8'b01000000;
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default : res = 8'b10000000;
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endcase // case(sel)
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end // always @ (sel or res)
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endmodule // decoder_3_8
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