mirror of
https://github.com/fairwaves/UHD-Fairwaves.git
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124 lines
4.3 KiB
Verilog
124 lines
4.3 KiB
Verilog
// Modified from code originally by Richard Herveille, his copyright is below
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// OpenCores Simple General Purpose IO core ////
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//// ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2002 Richard Herveille ////
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//// richard@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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module nsgpio16LE
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(input clk_i, input rst_i,
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input cyc_i, input stb_i, input [3:0] adr_i, input we_i, input [15:0] dat_i,
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output reg [15:0] dat_o, output reg ack_o,
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input [31:0] atr, input [31:0] debug_0, input [31:0] debug_1,
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inout [31:0] gpio
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);
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reg [31:0] ctrl, line, ddr, dbg, lgpio;
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wire wb_acc = cyc_i & stb_i; // WISHBONE access
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wire wb_wr = wb_acc & we_i; // WISHBONE write access
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always @(posedge clk_i or posedge rst_i)
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if (rst_i)
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begin
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ctrl <= 32'h0;
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line <= 32'h0;
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ddr <= 32'h0;
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dbg <= 32'h0;
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end
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else if (wb_wr)
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case( adr_i[3:1] )
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3'b000 :
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line[15:0] <= dat_i;
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3'b001 :
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line[31:16] <= dat_i;
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3'b010 :
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ddr[15:0] <= dat_i;
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3'b011 :
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ddr[31:16] <= dat_i;
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3'b100 :
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ctrl[15:0] <= dat_i;
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3'b101 :
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ctrl[31:16] <= dat_i;
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3'b110 :
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dbg[15:0] <= dat_i;
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3'b111 :
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dbg[31:16] <= dat_i;
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endcase // case ( adr_i[3:1] )
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always @(posedge clk_i)
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case (adr_i[3:1])
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3'b000 :
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dat_o <= lgpio[15:0];
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3'b001 :
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dat_o <= lgpio[31:16];
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3'b010 :
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dat_o <= ddr[15:0];
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3'b011 :
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dat_o <= ddr[31:16];
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3'b100 :
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dat_o <= ctrl[15:0];
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3'b101 :
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dat_o <= ctrl[31:16];
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3'b110 :
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dat_o <= dbg[15:0];
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3'b111 :
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dat_o <= dbg[31:16];
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endcase // case (adr_i[3:1])
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always @(posedge clk_i or posedge rst_i)
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if (rst_i)
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ack_o <= 1'b0;
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else
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ack_o <= wb_acc & !ack_o;
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// latch GPIO input pins
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always @(posedge clk_i)
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lgpio <= gpio;
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// assign GPIO outputs
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integer n;
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reg [31:0] igpio; // temporary internal signal
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always @(ctrl or line or debug_1 or debug_0 or atr or ddr or dbg)
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for(n=0;n<32;n=n+1)
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igpio[n] <= ddr[n] ? (dbg[n] ? (ctrl[n] ? debug_1[n] : debug_0[n]) :
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(ctrl[n] ? atr[n] : line[n]) )
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: 1'bz;
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assign gpio = igpio;
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endmodule
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