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93 lines
3.1 KiB
Verilog
93 lines
3.1 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// Dual ported, Harvard architecture, cached ram
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module ram_harv_cache
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#(parameter AWIDTH=15,parameter RAM_SIZE=16384,parameter ICWIDTH=6,parameter DCWIDTH=6)
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(input wb_clk_i, input wb_rst_i,
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input [AWIDTH-1:0] ram_loader_adr_i,
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input [31:0] ram_loader_dat_i,
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input ram_loader_stb_i,
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input [3:0] ram_loader_sel_i,
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input ram_loader_we_i,
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output ram_loader_ack_o,
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input ram_loader_done_i,
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input [AWIDTH-1:0] iwb_adr_i,
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input iwb_stb_i,
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output [31:0] iwb_dat_o,
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output iwb_ack_o,
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input [AWIDTH-1:0] dwb_adr_i,
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input [31:0] dwb_dat_i,
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output [31:0] dwb_dat_o,
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input dwb_we_i,
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output dwb_ack_o,
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input dwb_stb_i,
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input [3:0] dwb_sel_i,
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input flush_icache );
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wire [31:0] iram_dat, dram_dat_i, dram_dat_o;
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wire [AWIDTH-1:0] iram_adr, dram_adr;
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wire iram_en, dram_en, dram_we;
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wire [3:0] dram_sel;
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dpram32 #(.AWIDTH(AWIDTH),.RAM_SIZE(RAM_SIZE)) sys_ram
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(.clk(wb_clk_i),
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.adr1_i(ram_loader_done_i ? iram_adr : ram_loader_adr_i),
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.dat1_i(ram_loader_dat_i),
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.dat1_o(iram_dat),
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.we1_i(ram_loader_done_i ? 1'b0 : ram_loader_we_i),
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.en1_i(ram_loader_done_i ? iram_en : ram_loader_stb_i),
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.sel1_i(ram_loader_done_i ? 4'hF : ram_loader_sel_i),
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.adr2_i(dram_adr),.dat2_i(dram_dat_i),.dat2_o(dram_dat_o),
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.we2_i(dram_we),.en2_i(dram_en),.sel2_i(dram_sel) );
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// Data bus side
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dcache #(.AWIDTH(AWIDTH),.CWIDTH(DCWIDTH))
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dcache(.wb_clk_i(wb_clk_i),.wb_rst_i(wb_rst_i),
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.dwb_adr_i(dwb_adr_i),.dwb_stb_i(dwb_stb_i),
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.dwb_we_i(dwb_we_i),.dwb_sel_i(dwb_sel_i),
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.dwb_dat_i(dwb_dat_i),.dwb_dat_o(dwb_dat_o),
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.dwb_ack_o(dwb_ack_o),
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.dram_dat_i(dram_dat_o),.dram_dat_o(dram_dat_i),.dram_adr_o(dram_adr),
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.dram_we_o(dram_we),.dram_en_o(dram_en), .dram_sel_o(dram_sel) );
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// Instruction bus side
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icache #(.AWIDTH(AWIDTH),.CWIDTH(ICWIDTH))
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icache(.wb_clk_i(wb_clk_i),.wb_rst_i(wb_rst_i),
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.iwb_adr_i(iwb_adr_i),.iwb_stb_i(iwb_stb_i),
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.iwb_dat_o(iwb_dat_o),.iwb_ack_o(iwb_ack_o),
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.iram_dat_i(iram_dat),.iram_adr_o(iram_adr),.iram_en_o(iram_en),
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.flush(flush_icache));
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// RAM loader
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assign ram_loader_ack_o = ram_loader_stb_i;
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// Performance Monitoring
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wire i_wait = iwb_stb_i & ~iwb_ack_o;
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wire d_wait = dwb_stb_i & ~dwb_ack_o;
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endmodule // ram_harv_cache
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