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75 lines
2.1 KiB
Verilog
75 lines
2.1 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// wb_bus_writer
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//
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// WB Bus Master device to send a sequence of single-word transactions
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// based on a list in a RAM or ROM (FASM interface)
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// ROM data format is {WB_ADDR[15:0],WB_DATA[31:0]}
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// continues until it gets an all-1s entry
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module wb_bus_writer (input start,
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output done,
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output reg [15:0] rom_addr,
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input [47:0] rom_data,
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// WB Master Interface, don't need wb_dat_i
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input wb_clk_i,
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input wb_rst_i,
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output [31:0] wb_dat_o,
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input wb_ack_i,
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output [15:0] wb_adr_o,
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output wb_cyc_o,
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output [3:0] wb_sel_o,
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output wb_stb_o,
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output wb_we_o
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);
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`define IDLE 0
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`define READ 1
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reg [3:0] state;
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assign done = (state != `IDLE) && (&rom_data); // Done when we see all 1s
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always @(posedge wb_clk_i)
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if(wb_rst_i)
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begin
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rom_addr <= #1 0;
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state <= #1 0;
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end
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else if(start)
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begin
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rom_addr <= #1 0;
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state <= #1 `READ;
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end
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else if((state == `READ) && wb_ack_i)
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if(done)
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state <= #1 `IDLE;
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else
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rom_addr <= #1 rom_addr + 1;
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assign wb_dat_o = rom_data[31:0];
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assign wb_adr_o = rom_data[47:32];
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assign wb_sel_o = 4'b1111; // All writes are the full 32 bits
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assign wb_cyc_o = !done & (state != `IDLE);
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assign wb_stb_o = !done & (state != `IDLE);
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assign wb_we_o = !done & (state != `IDLE);
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endmodule // wb_bus_writer
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