mirror of
https://github.com/fairwaves/UHD-Fairwaves.git
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153 lines
4.6 KiB
Verilog
153 lines
4.6 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module icache
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#(parameter AWIDTH=14,
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parameter CWIDTH=6)
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(input wb_clk_i,
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input wb_rst_i,
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input [AWIDTH-1:0] iwb_adr_i,
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input iwb_stb_i,
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output [31:0] iwb_dat_o,
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output iwb_ack_o,
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input [31:0] iram_dat_i,
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output [AWIDTH-1:0] iram_adr_o,
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output iram_en_o,
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input flush);
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localparam TAGWIDTH = AWIDTH-CWIDTH-2;
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reg stb_d1, ack_d1, miss_d1;
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reg [AWIDTH-1:0] held_addr;
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reg [31:0] idata [0:(1<<CWIDTH)-1];
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reg [TAGWIDTH-1:0] itags [0:(1<<CWIDTH)-1];
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reg ivalid [0:(1<<CWIDTH)-1];
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wire [CWIDTH-1:0] rd_line, wr_line;
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wire [TAGWIDTH-1:0] wr_tags;
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wire store_in_cache;
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// /////////////////////////////////////
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// Write into cache
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integer i;
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always @(posedge wb_clk_i)
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if(wb_rst_i | flush)
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for(i=0;i<(1<<CWIDTH);i=i+1)
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ivalid[i] <= 0;
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else
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if(store_in_cache)
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ivalid[wr_line] <= 1'b1;
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always @(posedge wb_clk_i)
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if(store_in_cache)
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begin
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idata[wr_line] <= iram_dat_i;
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itags[wr_line] <= wr_tags;
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end
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// //////////////////////////////////////
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// Read from Cache
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wire [TAGWIDTH-1:0] tag_out = itags[rd_line];
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wire valid_out = ivalid[rd_line];
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wire [31:0] data_out = idata[rd_line];
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wire cache_hit = valid_out & (tag_out == iwb_adr_i[AWIDTH-1:CWIDTH+2]);
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wire cache_miss = ~cache_hit;
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// //////////////////////////////////////
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// Handle 1-cycle delay of Block-RAM
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always @(posedge wb_clk_i)
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if(wb_rst_i)
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stb_d1 <= 0;
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else
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stb_d1 <= iwb_stb_i;
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always @(posedge wb_clk_i)
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if(wb_rst_i)
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held_addr <= 0;
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else
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held_addr <= iwb_adr_i;
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always @(posedge wb_clk_i)
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if(wb_rst_i)
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ack_d1 <= 1'b0;
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else
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ack_d1 <= iwb_ack_o;
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always @(posedge wb_clk_i)
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if(wb_rst_i)
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miss_d1 <= 0;
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else
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miss_d1 <= cache_miss;
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//`define IC_NOCACHE
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//`define IC_BASIC
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//`define IC_FORWARDING_DP
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`define IC_FORWARDING_SP
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//`define IC_PREFETCH
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`ifdef IC_NOCACHE
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assign iwb_dat_o = iram_dat_i;
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assign iwb_ack_o = iwb_stb_i & (stb_d1 & ~ack_d1);
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assign iram_adr_o = iwb_adr_i;
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assign iram_en_o = 1'b1;
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assign rd_line = 0;
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assign wr_line = 0;
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assign wr_tags = 0;
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assign store_in_cache = 0;
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`endif
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`ifdef IC_BASIC // Very basic, no forwarding, 2 wait states on miss
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assign iwb_dat_o = data_out;
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assign iwb_ack_o = iwb_stb_i & cache_hit;
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assign iram_adr_o = iwb_adr_i;
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assign iram_en_o = 1'b1;
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assign rd_line = iwb_adr_i[CWIDTH+1:2];
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assign wr_line = rd_line;
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assign wr_tags = iwb_adr_i[AWIDTH-1:CWIDTH+2];
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assign store_in_cache = stb_d1 & miss_d1;
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`endif
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`ifdef IC_FORWARDING_DP // Simple forwarding, 1 wait state on miss, dual-port ram
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assign iwb_dat_o = cache_hit ? data_out : iram_dat_i;
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assign iwb_ack_o = iwb_stb_i & (cache_hit | (stb_d1 & ~ack_d1));
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assign iram_adr_o = iwb_adr_i;
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assign iram_en_o = 1'b1;
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assign rd_line = iwb_adr_i[CWIDTH+1:2];
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assign wr_line = held_addr[CWIDTH+1:2];
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assign wr_tags = held_addr[AWIDTH-1:CWIDTH+2];
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assign store_in_cache = iwb_stb_i & stb_d1 & miss_d1 & ~ack_d1;
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`endif
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`ifdef IC_FORWARDING_SP // Simple forwarding, 1 wait state on miss, single-port ram
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assign iwb_dat_o = cache_hit ? data_out : iram_dat_i;
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assign iwb_ack_o = iwb_stb_i & (cache_hit | (stb_d1 & ~ack_d1));
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assign iram_adr_o = iwb_adr_i;
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assign iram_en_o = 1'b1;
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assign rd_line = iwb_adr_i[CWIDTH+1:2];
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assign wr_line = rd_line;
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assign wr_tags = iwb_adr_i[AWIDTH-1:CWIDTH+2];
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assign store_in_cache = iwb_stb_i & stb_d1 & miss_d1 & ~ack_d1;
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`endif
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`ifdef IC_PREFETCH // Forwarding plus prefetch
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`endif
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endmodule // icache
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