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64 lines
1.8 KiB
Verilog
64 lines
1.8 KiB
Verilog
//
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// Copyright 2012 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// User settings bus
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//
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// Provides 8-bit address, 32-bit data write only bus for user settings, consumes to addresses in
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// normal settings bus.
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//
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// Write user address to BASE
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// Write user data to BASE+1
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//
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// The user_set_stb will strobe after data write, must write new address even if same as previous one.
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module user_settings
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#(parameter BASE=0)
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(input clk,
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input rst,
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input set_stb,
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input [7:0] set_addr,
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input [31:0] set_data,
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output set_stb_user,
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output [7:0] set_addr_user,
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output [31:0] set_data_user
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);
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wire addr_changed, data_changed;
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reg stb_int;
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setting_reg #(.my_addr(BASE+0),.width(8)) sr_0
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(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out(set_addr_user),.changed(addr_changed) );
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setting_reg #(.my_addr(BASE+1)) sr_1
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(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out(set_data_user),.changed(data_changed) );
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always @(posedge clk)
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if (rst|set_stb_user)
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stb_int <= 0;
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else
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if (addr_changed)
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stb_int <= 1;
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assign set_stb_user = stb_int & data_changed;
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endmodule // user_settings
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