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72 lines
2.0 KiB
Verilog
72 lines
2.0 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module v5icap_wb
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(input clk, input reset,
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input cyc_i, input stb_i, input we_i, output ack_o,
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input [31:0] dat_i, output [31:0] dat_o);
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wire BUSY, CE, WRITE;
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reg [2:0] icap_state;
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localparam ICAP_IDLE = 0;
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localparam ICAP_WR0 = 1;
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localparam ICAP_WR1 = 2;
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localparam ICAP_RD0 = 3;
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localparam ICAP_RD1 = 4;
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always @(posedge clk)
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if(reset)
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icap_state <= ICAP_IDLE;
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else
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case(icap_state)
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ICAP_IDLE :
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begin
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if(stb_i & cyc_i)
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if(we_i)
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icap_state <= ICAP_WR0;
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else
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icap_state <= ICAP_RD0;
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end
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ICAP_WR0 :
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icap_state <= ICAP_WR1;
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ICAP_WR1 :
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icap_state <= ICAP_IDLE;
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ICAP_RD0 :
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icap_state <= ICAP_RD1;
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ICAP_RD1 :
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icap_state <= ICAP_IDLE;
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endcase // case (icap_state)
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assign WRITE = (icap_state == ICAP_WR0) | (icap_state == ICAP_WR1);
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assign CE = (icap_state == ICAP_WR1) | (icap_state == ICAP_RD0);
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assign ack_o = (icap_state == ICAP_WR1) | (icap_state == ICAP_RD1);
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ICAP_VIRTEX5 #(.ICAP_WIDTH("X32")) ICAP_VIRTEX5_inst
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(.BUSY(BUSY), // Busy output
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.O(dat_o), // 32-bit data output
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.CE(~CE), // Clock enable input
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.CLK(clk), // Clock input
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.I(dat_i), // 32-bit data input
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.WRITE(~WRITE) // Write input
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);
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endmodule // v5icap_wb
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