mirror of
https://github.com/fairwaves/UHD-Fairwaves.git
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97 lines
2.3 KiB
Verilog
97 lines
2.3 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module wb_sim();
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wire wb_clk, wb_rst;
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wire start;
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reg POR, aux_clk, clk_fpga;
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initial POR = 1'b1;
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initial #103 POR = 1'b0;
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initial aux_clk = 1'b0;
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always #25 aux_clk = ~aux_clk;
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initial clk_fpga = 1'bx;
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initial #3007 clk_fpga = 1'b0;
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always #7 clk_fpga = ~clk_fpga;
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initial begin
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$dumpfile("wb_sim.vcd");
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$dumpvars(0,wb_sim);
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end
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initial #10000 $finish;
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wire [15:0] rom_addr;
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wire [47:0] rom_data;
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wire [31:0] wb_dat;
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wire [15:0] wb_adr;
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wire wb_cyc,wb_stb,wb_we,wb_ack;
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wire [3:0] wb_sel;
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wire [31:0] port_output;
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system_control system_control(.dsp_clk(dsp_clk),
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.reset_out(reset_out),
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.wb_clk_o(wb_clk),
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.wb_rst_o(wb_rst),
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.wb_rst_o_alt(wb_rst_o_alt),
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.start (start),
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.aux_clk(aux_clk),
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.clk_fpga(clk_fpga),
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.POR (POR),
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.done (done));
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clock_bootstrap_rom cbrom(.addr(rom_addr),.data(rom_data));
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wb_bus_writer bus_writer(.rom_addr (rom_addr[15:0]),
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.wb_dat_o (wb_dat[31:0]),
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.wb_adr_o (wb_adr[15:0]),
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.wb_cyc_o (wb_cyc),
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.wb_sel_o (wb_sel[3:0]),
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.wb_stb_o (wb_stb),
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.wb_we_o (wb_we),
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.start (start),
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.done (done),
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.rom_data (rom_data[47:0]),
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.wb_clk_i (wb_clk),
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.wb_rst_i (wb_rst),
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.wb_ack_i (wb_ack));
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wb_output_pins32 output_pins(.wb_dat_o(),
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.wb_ack_o(wb_ack),
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.port_output(port_output[31:0]),
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.wb_rst_i(wb_rst),
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.wb_clk_i(wb_clk),
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.wb_dat_i(wb_dat[31:0]),
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.wb_we_i(wb_we),
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.wb_sel_i(wb_sel[3:0]),
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.wb_stb_i(wb_stb),
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.wb_cyc_i(wb_cyc));
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endmodule // wb_sim
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