mirror of
https://github.com/fairwaves/UHD-Fairwaves.git
synced 2025-11-03 05:23:14 +00:00
436 lines
9.5 KiB
Verilog
436 lines
9.5 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module buffer_int_tb ();
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reg clk = 0;
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reg rst = 1;
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initial #100 rst = 0;
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always #5 clk = ~clk;
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wire en, we;
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wire [8:0] addr;
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wire [31:0] fifo2buf, buf2fifo;
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wire [31:0] rd_data_o;
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wire [3:0] rd_flags_o;
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wire rd_sop_o, rd_eop_o;
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reg rd_error_i = 0, rd_read_i = 0;
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reg [31:0] wr_data_i = 0;
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wire [3:0] wr_flags_i;
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reg wr_eop_i = 0, wr_sop_i = 0;
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reg wr_write_i = 0;
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wire wr_ready_o, wr_full_o;
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reg clear = 0, write = 0, read = 0;
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reg [8:0] firstline = 0, lastline = 0;
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wire [3:0] step = 1;
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wire [31:0] ctrl_word = {4'b0,3'b0,clear,write,read,step,lastline,firstline};
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reg go = 0;
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wire done, error;
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assign wr_flags_i = {2'b00, wr_eop_i, wr_sop_i};
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assign rd_sop_o = rd_flags_o[0];
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assign rd_eop_o = rd_flags_o[1];
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buffer_int buffer_int
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(.clk(clk),.rst(rst),
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.ctrl_word(ctrl_word),.go(go),
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.done(done),.error(error),
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// Buffer Interface
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.en_o(en),.we_o(we),.addr_o(addr),
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.dat_to_buf(fifo2buf),.dat_from_buf(buf2fifo),
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// Write FIFO Interface
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.wr_data_i(wr_data_i), .wr_flags_i(wr_flags_i), .wr_write_i(wr_write_i), .wr_ready_o(wr_ready_o),
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// Read FIFO Interface
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.rd_data_o(rd_data_o), .rd_flags_o(rd_flags_o), .rd_ready_o(rd_ready_o), .rd_read_i(rd_read_i)
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);
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reg ram_en = 0, ram_we = 0;
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reg [8:0] ram_addr = 0;
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reg [31:0] ram_data = 0;
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ram_2port #(.DWIDTH(32),.AWIDTH(9)) ram_2port
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(.clka(clk), .ena(ram_en), .wea(ram_we), .addra(ram_addr), .dia(ram_data), .doa(),
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.clkb(clk), .enb(en), .web(we), .addrb(addr), .dib(fifo2buf), .dob(buf2fifo) );
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initial
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begin
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@(negedge rst);
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@(posedge clk);
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FillRAM;
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ResetBuffer;
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SetBufferRead(5,10);
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$display("Testing full read, no wait states.");
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while(!rd_sop_o)
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@(posedge clk);
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ReadLines(6,0);
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repeat (10)
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@(posedge clk);
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ResetBuffer;
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SetBufferRead(5,10);
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$display("Testing full read, 2 wait states.");
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while(!rd_sop_o)
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@(posedge clk);
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ReadLines(6,2);
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repeat (10)
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@(posedge clk);
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ResetBuffer;
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SetBufferRead(5,10);
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$display("Testing partial read, 0 wait states, then nothing after last.");
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while(!rd_sop_o)
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@(posedge clk);
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ReadLines(3,0);
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repeat (10)
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@(posedge clk);
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ResetBuffer;
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SetBufferRead(5,10);
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$display("Testing partial read, 0 wait states, then done at same time as last.");
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while(!rd_sop_o)
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@(posedge clk);
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ReadLines(2,0);
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ReadALine;
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repeat (10)
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@(posedge clk);
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ResetBuffer;
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SetBufferRead(5,10);
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$display("Testing partial read, 3 wait states, then error at same time as last.");
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while(!rd_sop_o)
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@(posedge clk);
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ReadLines(2,3);
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rd_error_i <= 1;
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ReadALine;
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rd_error_i <= 0;
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repeat (10)
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@(posedge clk);
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ResetBuffer;
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SetBufferRead(500,511);
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$display("Testing full read, to the end of the buffer.");
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while(!rd_sop_o)
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@(posedge clk);
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ReadLines(12,0);
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repeat (10)
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@(posedge clk);
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ResetBuffer;
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SetBufferRead(0,511);
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$display("Testing full read, start to end of the buffer.");
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while(!rd_sop_o)
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@(posedge clk);
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ReadLines(512,0);
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repeat (10)
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@(posedge clk);
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ResetBuffer;
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SetBufferRead(505,3);
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$display("Testing full read, wraparound");
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while(!rd_sop_o)
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@(posedge clk);
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ReadLines(11,0);
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repeat (10)
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@(posedge clk);
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ResetBuffer;
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SetBufferWrite(10,15);
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$display("Testing Full Write, no wait states");
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while(!wr_ready_o)
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@(posedge clk);
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WriteLines(6,0,72);
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repeat (10)
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@(posedge clk);
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ResetBuffer;
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SetBufferWrite(18,23);
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$display("Testing Full Write, 1 wait states");
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while(!wr_ready_o)
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@(posedge clk);
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WriteLines(6,1,101);
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repeat (10)
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@(posedge clk);
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ResetBuffer;
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SetBufferWrite(27,40);
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$display("Testing Partial Write, 0 wait states");
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while(!wr_ready_o)
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@(posedge clk);
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WriteLines(6,0,201);
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repeat (10)
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@(posedge clk);
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ResetBuffer;
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SetBufferWrite(45,200);
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$display("Testing Partial Write, 0 wait states, then done and write simultaneously");
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while(!wr_ready_o)
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@(posedge clk);
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wr_sop_i <= 1; wr_eop_i <= 0;
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WriteLines(6,0,301);
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wr_sop_i <= 0; wr_eop_i <= 1;
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WriteALine(400);
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wr_sop_i <= 0; wr_eop_i <= 0;
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repeat (10)
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@(posedge clk);
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ResetBuffer;
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SetBufferWrite(55,200);
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$display("Testing Partial Write, 0 wait states, then error");
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while(!wr_ready_o)
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@(posedge clk);
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WriteLines(6,0,501);
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wr_sop_i <= 1; wr_eop_i <= 1;
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WriteALine(400);
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@(posedge clk);
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repeat (10)
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@(posedge clk);
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wr_sop_i <= 0; wr_eop_i <= 0;
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ResetBuffer;
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SetBufferRead(0,82);
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$display("Testing read after all the writes");
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while(!rd_sop_o)
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@(posedge clk);
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ReadLines(83,0);
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repeat (10)
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@(posedge clk);
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ResetBuffer;
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SetBufferWrite(508,4);
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$display("Testing wraparound write");
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while(!wr_ready_o)
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@(posedge clk);
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WriteLines(9,0,601);
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repeat (10)
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@(posedge clk);
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ResetBuffer;
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SetBufferRead(506,10);
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$display("Reading wraparound write");
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while(!rd_sop_o)
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@(posedge clk);
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ReadLines(17,0);
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repeat (10)
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@(posedge clk);
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ResetBuffer;
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SetBufferWrite(0,511);
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$display("Testing Whole Buffer write");
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while(!wr_ready_o)
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@(posedge clk);
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WriteLines(512,0,1000);
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repeat (10)
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@(posedge clk);
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ResetBuffer;
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SetBufferRead(0,511);
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$display("Reading Whole Buffer write");
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while(!rd_sop_o)
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@(posedge clk);
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ReadLines(512,0);
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repeat (10)
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@(posedge clk);
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/*
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ResetBuffer;
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SetBufferWrite(5,10);
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$display("Testing Write Too Many");
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while(!wr_ready_o)
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@(posedge clk);
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WriteLines(12,0,2000);
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repeat (10)
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@(posedge clk);
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ResetBuffer;
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SetBufferRead(0,15);
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$display("Reading back Write Too Many");
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while(!rd_sop_o)
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@(posedge clk);
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ReadLines(16,0);
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repeat (10)
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@(posedge clk);
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*/
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ResetBuffer;
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SetBufferWrite(15,20);
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$display("Testing Write One Less Than Full");
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while(!wr_ready_o)
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@(posedge clk);
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wr_sop_i <= 1; wr_eop_i <= 0;
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WriteALine(400);
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wr_sop_i <= 0; wr_eop_i <= 0;
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WriteLines(3,0,2000);
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wr_sop_i <= 0; wr_eop_i <= 1;
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WriteALine(400);
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wr_sop_i <= 0; wr_eop_i <= 0;
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repeat (10)
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@(posedge clk);
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ResetBuffer;
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SetBufferRead(13,22);
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$display("Reading back Write One Less Than Full");
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while(!rd_sop_o)
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@(posedge clk);
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ReadLines(10,0);
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repeat (10)
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@(posedge clk);
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ResetBuffer;
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repeat(100)
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@(posedge clk);
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$finish;
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end
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always @(posedge clk)
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if(rd_read_i == 1'd1)
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$display("READ Buffer %d, rd_sop_o %d, rd_eop_o %d", rd_data_o, rd_sop_o, rd_eop_o);
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always @(posedge clk)
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if(wr_write_i == 1'd1)
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$display("WRITE Buffer %d, wr_ready_o %d, wr_full_o %d", wr_data_i, wr_ready_o, wr_full_o);
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initial begin
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$dumpfile("buffer_int_tb.lxt");
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$dumpvars(0,buffer_int_tb);
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end
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task FillRAM;
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begin
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ram_addr <= 0;
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ram_data <= 0;
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@(posedge clk);
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ram_en <= 1;
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ram_we <= 1;
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@(posedge clk);
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repeat (511)
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begin
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ram_addr <= ram_addr + 1;
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ram_data <= ram_data + 1;
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ram_en <= 1;
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ram_we <= 1;
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@(posedge clk);
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end
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ram_en <= 0;
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ram_we <= 0;
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@(posedge clk);
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$display("Filled the RAM");
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end
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endtask // FillRAM
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task ResetBuffer;
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begin
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clear <= 1; read <= 0; write <= 0;
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go <= 1;
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@(posedge clk);
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go <= 0;
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@(posedge clk);
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$display("Buffer Reset");
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end
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endtask // ClearBuffer
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task SetBufferWrite;
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input [8:0] start;
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input [8:0] stop;
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begin
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clear <= 0; read <= 0; write <= 1;
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firstline <= start;
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lastline <= stop;
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go <= 1;
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@(posedge clk);
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go <= 0;
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@(posedge clk);
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$display("Buffer Set for Write");
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end
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endtask // SetBufferWrite
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task SetBufferRead;
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input [8:0] start;
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input [8:0] stop;
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begin
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clear <= 0; read <= 1; write <= 0;
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firstline <= start;
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lastline <= stop;
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go <= 1;
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@(posedge clk);
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go <= 0;
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@(posedge clk);
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$display("Buffer Set for Read");
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end
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endtask // SetBufferRead
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task ReadALine;
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begin
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while(~rd_ready_o)
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@(posedge clk);
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#1 rd_read_i <= 1;
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@(posedge clk);
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rd_read_i <= 0;
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end
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endtask // ReadALine
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task ReadLines;
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input [9:0] lines;
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input [7:0] wait_states;
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begin
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$display("Read Lines: Number %d, Wait States %d",lines,wait_states);
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repeat (lines)
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begin
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ReadALine;
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repeat (wait_states)
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@(posedge clk);
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end
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end
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endtask // ReadLines
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task WriteALine;
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input [31:0] value;
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begin
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while(~wr_ready_o)
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@(posedge clk);
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#1 wr_write_i <= 1;
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wr_data_i <= value;
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@(posedge clk);
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wr_write_i <= 0;
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end
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endtask // WriteALine
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task WriteLines;
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input [9:0] lines;
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input [7:0] wait_states;
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input [31:0] value;
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begin
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$display("Write Lines: Number %d, Wait States %d",lines,wait_states);
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repeat(lines)
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begin
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value <= value + 1;
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WriteALine(value);
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repeat(wait_states)
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@(posedge clk);
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end
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end
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endtask // WriteLines
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endmodule // buffer_int_tb
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