mirror of
https://github.com/fairwaves/UHD-Fairwaves.git
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137 lines
3.7 KiB
Verilog
137 lines
3.7 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module fifo_to_wb_tb();
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reg clk = 0;
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reg rst = 1;
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reg clear = 0;
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initial #1000 rst = 0;
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always #50 clk = ~clk;
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reg trigger = 0;
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initial #10000 trigger = 1;
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wire wb_cyc, wb_stb, wb_we, wb_ack;
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wire [15:0] wb_adr;
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wire [15:0] wb_dat_miso, wb_dat_mosi;
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reg cmd_src_rdy;
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wire cmd_dst_rdy, resp_src_rdy, resp_dst_rdy;
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reg [17:0] cmd;
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wire [17:0] resp;
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wire [17:0] resp_int;
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wire resp_src_rdy_int, resp_dst_rdy_int;
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fifo_to_wb fifo_to_wb
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(.clk(clk), .reset(rst), .clear(clear),
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.data_i(cmd), .src_rdy_i(cmd_src_rdy), .dst_rdy_o(cmd_dst_rdy),
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.data_o(resp_int), .src_rdy_o(resp_src_rdy_int), .dst_rdy_i(resp_dst_rdy_int),
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.wb_adr_o(wb_adr), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso),
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.wb_sel_o(), .wb_cyc_o(wb_cyc), .wb_stb_o(wb_stb),
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.wb_we_o(wb_we), .wb_ack_i(wb_ack),
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.triggers());
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assign wb_dat_miso = {wb_adr[7:0],8'hBF};
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fifo19_pad #(.LENGTH(16)) fifo19_pad
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(.clk(clk), .reset(rst), .clear(clear),
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.data_i(resp_int), .src_rdy_i(resp_src_rdy_int), .dst_rdy_o(resp_dst_rdy_int),
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.data_o(resp), .src_rdy_o(resp_src_rdy), .dst_rdy_i(resp_dst_rdy));
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// Set up monitors
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always @(posedge clk)
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if(wb_cyc & wb_stb & wb_ack)
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if(wb_we)
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$display("WB-WRITE ADDR:%h DATA:%h",wb_adr, wb_dat_mosi);
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else
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$display("WB-READ ADDR:%h DATA:%h",wb_adr, wb_dat_miso);
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always @(posedge clk)
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if(cmd_src_rdy & cmd_dst_rdy)
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$display("CMD-WRITE SOF:%b EOF:%b DATA:%h",cmd[16],cmd[17],cmd[15:0]);
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always @(posedge clk)
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if(resp_src_rdy & resp_dst_rdy)
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$display("RESP-READ SOF:%b EOF:%b DATA:%h",resp[16],resp[17],resp[15:0]);
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assign wb_ack = wb_stb;
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assign resp_dst_rdy = 1;
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task InsertRW;
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input [15:0] data_start;
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input [5:0] triggers;
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input [7:0] seqno;
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input [15:0] len;
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input [15:0] addr;
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reg [15:0] data_val;
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begin
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data_val <= data_start;
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@(posedge clk);
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cmd <= {2'b01,2'b11,triggers,seqno};
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cmd_src_rdy <= 1;
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@(posedge clk);
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cmd <= {2'b00,len};
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@(posedge clk);
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cmd <= {2'b00,addr};
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@(posedge clk);
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cmd <= {2'b00,16'd0};
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@(posedge clk);
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repeat (len)
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begin
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cmd <= {2'b00,data_val};
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data_val <= data_val + 1;
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@(posedge clk);
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end
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repeat (12-len-1)
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begin
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cmd <= {2'b00,16'hBEEF};
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@(posedge clk);
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end
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cmd <= {2'b10, 16'hDEAD};
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@(posedge clk);
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cmd_src_rdy <= 0;
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end
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endtask // InsertRead
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initial $dumpfile("fifo_to_wb_tb.vcd");
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initial $dumpvars(0,fifo_to_wb_tb);
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initial
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begin
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@(negedge rst);
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//#10000;
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@(posedge clk);
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@(posedge clk);
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@(posedge clk);
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@(posedge clk);
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InsertRW(16'hF00D, 6'd0, 8'hB5, 16'd7, 16'h1234);
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#20000;
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InsertRW(16'h9876, 6'd0, 8'h43, 16'd8, 16'hBEEF);
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#20000;
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InsertRW(16'h1000, 6'd0, 8'h96, 16'd4, 16'hF00D);
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#20000;
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InsertRW(16'h3000, 6'd0, 8'h12, 16'd10,16'hDEAD);
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#20000 $finish;
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end
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endmodule // fifo_to_wb_tb
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