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https://github.com/fairwaves/UHD-Fairwaves.git
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67 lines
2.1 KiB
Verilog
67 lines
2.1 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module medfifo
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#(parameter WIDTH=32,
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parameter DEPTH=1)
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(input clk, input rst,
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input [WIDTH-1:0] datain,
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output [WIDTH-1:0] dataout,
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input read,
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input write,
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input clear,
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output full,
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output empty,
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output [7:0] space,
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output [7:0] occupied);
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localparam NUM_FIFOS = (1<<DEPTH);
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wire [WIDTH-1:0] dout [0:NUM_FIFOS-1];
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wire [0:NUM_FIFOS-1] full_x;
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wire [0:NUM_FIFOS-1] empty_x;
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shortfifo #(.WIDTH(WIDTH))
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head (.clk(clk),.rst(rst),
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.datain(datain),.write(write),.full(full),
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.dataout(dout[0]),.read(~empty_x[0] & ~full_x[1]),.empty(empty_x[0]),
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.clear(clear),.space(space[4:0]),.occupied() );
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shortfifo #(.WIDTH(WIDTH))
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tail (.clk(clk),.rst(rst),
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.datain(dout[NUM_FIFOS-2]),.write(~empty_x[NUM_FIFOS-2] & ~full_x[NUM_FIFOS-1]),.full(full_x[NUM_FIFOS-1]),
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.dataout(dataout),.read(read),.empty(empty),
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.clear(clear),.space(),.occupied(occupied[4:0]) );
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genvar i;
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generate
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for(i = 1; i < NUM_FIFOS-1 ; i = i + 1)
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begin : gen_depth
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shortfifo #(.WIDTH(WIDTH))
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shortfifo (.clk(clk),.rst(rst),
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.datain(dout[i-1]),.write(~full_x[i] & ~empty_x[i-1]),.full(full_x[i]),
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.dataout(dout[i]),.read(~full_x[i+1] & ~empty_x[i]),.empty(empty_x[i]),
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.clear(clear),.space(),.occupied() );
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end
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endgenerate
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assign space[7:5] = 0;
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assign occupied[7:5] = 0;
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endmodule // medfifo
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