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https://github.com/fairwaves/UHD-Fairwaves.git
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81 lines
3.0 KiB
Verilog
81 lines
3.0 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// Parameter LE tells us if we are little-endian.
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// Little-endian means send lower 16 bits first.
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// Default is big endian (network order), send upper bits first.
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module fifo72_to_fifo36
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#(parameter LE=0)
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(input clk, input reset, input clear,
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input [71:0] f72_datain,
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input f72_src_rdy_i,
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output f72_dst_rdy_o,
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output [35:0] f36_dataout,
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output f36_src_rdy_o,
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input f36_dst_rdy_i );
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wire [35:0] f36_data_int;
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wire f36_src_rdy_int, f36_dst_rdy_int;
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wire [71:0] f72_data_int;
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wire f72_src_rdy_int, f72_dst_rdy_int;
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// Shortfifo on input to guarantee no deadlock
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fifo_short #(.WIDTH(72)) head_fifo
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(.clk(clk),.reset(reset),.clear(clear),
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.datain(f72_datain), .src_rdy_i(f72_src_rdy_i), .dst_rdy_o(f72_dst_rdy_o),
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.dataout(f72_data_int), .src_rdy_o(f72_src_rdy_int), .dst_rdy_i(f72_dst_rdy_int),
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.space(),.occupied() );
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// Main fifo72_to_fifo36, needs shortfifos to guarantee no deadlock
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wire [2:0] f72_occ_int = f72_data_int[68:66];
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wire f72_sof_int = f72_data_int[64];
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wire f72_eof_int = f72_data_int[65];
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reg phase;
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wire half_line = f72_eof_int & ( (f72_occ_int==1)|(f72_occ_int==2)|(f72_occ_int==3)|(f72_occ_int==4) );
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assign f36_data_int[31:0] = (LE ^ phase) ? f72_data_int[31:0] : f72_data_int[63:32];
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assign f36_data_int[32] = phase ? 0 : f72_sof_int;
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assign f36_data_int[33] = phase ? f72_eof_int : half_line;
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assign f36_data_int[35:34] = f36_data_int[33] ? f72_occ_int[1:0] : 2'b00;
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assign f36_src_rdy_int = f72_src_rdy_int;
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assign f72_dst_rdy_int = (phase | half_line) & f36_dst_rdy_int;
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wire f36_xfer = f36_src_rdy_int & f36_dst_rdy_int;
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wire f72_xfer = f72_src_rdy_int & f72_dst_rdy_int;
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always @(posedge clk)
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if(reset)
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phase <= 0;
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else if(f72_xfer)
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phase <= 0;
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else if(f36_xfer)
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phase <= 1;
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// Shortfifo on output to guarantee no deadlock
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fifo_short #(.WIDTH(36)) tail_fifo
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(.clk(clk),.reset(reset),.clear(clear),
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.datain(f36_data_int), .src_rdy_i(f36_src_rdy_int), .dst_rdy_o(f36_dst_rdy_int),
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.dataout(f36_dataout), .src_rdy_o(f36_src_rdy_o), .dst_rdy_i(f36_dst_rdy_i),
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.space(),.occupied() );
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endmodule // fifo72_to_fifo36
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