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105 lines
3.4 KiB
Verilog
105 lines
3.4 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module ll8_to_fifo19
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(input clk, input reset, input clear,
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input [7:0] ll_data,
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input ll_sof,
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input ll_eof,
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input ll_src_rdy,
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output ll_dst_rdy,
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output [18:0] f19_data,
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output f19_src_rdy_o,
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input f19_dst_rdy_i );
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// Short FIFO on input to guarantee no deadlock
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wire [7:0] ll_data_int;
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wire ll_sof_int, ll_eof_int, ll_src_rdy_int, ll_dst_rdy_int;
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ll8_shortfifo head_fifo
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(.clk(clk), .reset(reset), .clear(clear),
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.datain(ll_data), .sof_i(ll_sof), .eof_i(ll_eof),
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.error_i(0), .src_rdy_i(ll_src_rdy), .dst_rdy_o(ll_dst_rdy),
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.dataout(ll_data_int), .sof_o(ll_sof_int), .eof_o(ll_eof_int),
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.error_o(), .src_rdy_o(ll_src_rdy_int), .dst_rdy_i(ll_dst_rdy_int));
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// Actual ll8_to_fifo19 which could deadlock if not connected to a shortfifo
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localparam XFER_EMPTY = 0;
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localparam XFER_HALF = 1;
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localparam XFER_HALF_WRITE = 3;
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wire [18:0] f19_data_int;
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wire f19_sof_int, f19_eof_int, f19_occ_int, f19_src_rdy_int, f19_dst_rdy_int;
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wire xfer_out = f19_src_rdy_int & f19_dst_rdy_int;
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wire xfer_in = ll_src_rdy_int & ll_dst_rdy_int;
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reg hold_sof;
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reg [1:0] state;
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reg [7:0] hold_reg;
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always @(posedge clk)
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if(ll_src_rdy_int & (state==XFER_EMPTY))
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hold_reg <= ll_data_int;
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always @(posedge clk)
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if(ll_sof_int & (state==XFER_EMPTY))
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hold_sof <= 1;
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else if(xfer_out)
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hold_sof <= 0;
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always @(posedge clk)
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if(reset | clear)
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state <= XFER_EMPTY;
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else
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case(state)
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XFER_EMPTY :
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if(ll_src_rdy_int)
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if(ll_eof_int)
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state <= XFER_HALF_WRITE;
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else
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state <= XFER_HALF;
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XFER_HALF :
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if(ll_src_rdy_int & f19_dst_rdy_int)
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state <= XFER_EMPTY;
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XFER_HALF_WRITE :
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if(f19_dst_rdy_int)
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state <= XFER_EMPTY;
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endcase // case (state)
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assign ll_dst_rdy_int = (state==XFER_EMPTY) | ((state==XFER_HALF)&f19_dst_rdy_int);
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assign f19_src_rdy_int= (state==XFER_HALF_WRITE) | ((state==XFER_HALF)&ll_src_rdy_int);
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assign f19_sof_int = hold_sof | (ll_sof_int & (state==XFER_HALF));
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assign f19_eof_int = (state == XFER_HALF_WRITE) | ll_eof_int;
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assign f19_occ_int = (state == XFER_HALF_WRITE);
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assign f19_data_int = {f19_occ_int,f19_eof_int,f19_sof_int,hold_reg,ll_data_int};
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// Shortfifo on output to guarantee no deadlock
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fifo_short #(.WIDTH(19)) tail_fifo
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(.clk(clk),.reset(reset),.clear(clear),
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.datain(f19_data_int), .src_rdy_i(f19_src_rdy_int), .dst_rdy_o(f19_dst_rdy_int),
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.dataout(f19_data), .src_rdy_o(f19_src_rdy_o), .dst_rdy_i(f19_dst_rdy_i),
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.space(),.occupied() );
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endmodule // ll8_to_fifo19
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