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60 lines
1.9 KiB
Verilog
60 lines
1.9 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// Adds a junk line at the beginning of every packet, which the
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// following stages should ignore. This gives us proper alignment due
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// to the 14 byte ethernet header
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// Bit 18 -- odd length
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// Bit 17 -- eof
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// Bit 16 -- sof
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// Bit 15:0 -- data
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module fifo19_rxrealign
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(input clk, input reset, input clear,
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input [18:0] datain, input src_rdy_i, output dst_rdy_o,
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output [18:0] dataout, output src_rdy_o, input dst_rdy_i);
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reg rxre_state;
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localparam RXRE_DUMMY = 0;
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localparam RXRE_PKT = 1;
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assign dataout[18] = datain[18];
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assign dataout[17] = datain[17];
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assign dataout[16] = (rxre_state==RXRE_DUMMY) | (datain[17] & datain[16]); // allows for passing error signal
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assign dataout[15:0] = datain[15:0];
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always @(posedge clk)
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if(reset | clear)
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rxre_state <= RXRE_DUMMY;
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else if(src_rdy_i & dst_rdy_i)
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case(rxre_state)
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RXRE_DUMMY :
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rxre_state <= RXRE_PKT;
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RXRE_PKT :
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if(datain[17]) // if eof or error
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rxre_state <= RXRE_DUMMY;
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endcase // case (rxre_state)
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assign src_rdy_o = src_rdy_i & dst_rdy_i; // Send anytime both sides are ready
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assign dst_rdy_o = src_rdy_i & dst_rdy_i & (rxre_state == RXRE_PKT); // Only consume after the dummy
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endmodule // fifo19_rxrealign
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