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182 lines
6.5 KiB
Verilog
Executable File
182 lines
6.5 KiB
Verilog
Executable File
// file: pll_clk.v
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//
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// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//----------------------------------------------------------------------------
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// User entered comments
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//----------------------------------------------------------------------------
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// None
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//
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//----------------------------------------------------------------------------
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// Output Output Phase Duty Cycle Pk-to-Pk Phase
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// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
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//----------------------------------------------------------------------------
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// CLK_OUT1 52.001 0.000 50.0 329.317 276.415
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// CLK_OUT2 104.001 0.000 50.0 289.929 276.415
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// CLK_OUT3 104.001 0.000 50.0 289.929 276.415
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// CLK_OUT4 104.001 270.000 50.0 289.929 276.415
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// CLK_OUT5 13.000 180.000 50.0 424.762 276.415
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// CLK_OUT6 26.000 0.000 50.0 374.029 276.415
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//
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//----------------------------------------------------------------------------
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// Input Clock Input Freq (MHz) Input Jitter (UI)
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//----------------------------------------------------------------------------
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// primary 26.000 0.0010
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`timescale 1ps/1ps
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(* CORE_GENERATION_INFO = "pll_clk,clk_wiz_v3_1,{component_name=pll_clk,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=6,clkin1_period=38.461,clkin2_period=38.461,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
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module pll_clk
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(// Clock in ports
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input clk_in,
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// Clock out ports
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output wb_clk,
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output clk_fpga,
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output dsp_clk,
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output clk270_100,
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output clk_icap,
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output lms_clk,
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// Status and control signals
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output LOCKED_OUT
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);
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// Input buffering
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//------------------------------------
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IBUFG clkin1_buf
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(.O (clkin1),
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.I (clk_in));
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// Clocking primitive
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//------------------------------------
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// Instantiation of the PLL primitive
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// * Unused inputs are tied off
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// * Unused outputs are labeled unused
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wire [15:0] do_unused;
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wire drdy_unused;
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wire clkfbout;
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wire clkfbout_buf;
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PLL_BASE
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#(.BANDWIDTH ("OPTIMIZED"),
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.CLK_FEEDBACK ("CLKFBOUT"),
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.COMPENSATION ("SYSTEM_SYNCHRONOUS"),
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.DIVCLK_DIVIDE (1),
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.CLKFBOUT_MULT (16),
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.CLKFBOUT_PHASE (0.000),
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.CLKOUT0_DIVIDE (8),
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.CLKOUT0_PHASE (0.000),
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.CLKOUT0_DUTY_CYCLE (0.500),
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.CLKOUT1_DIVIDE (4),
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.CLKOUT1_PHASE (0.000),
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.CLKOUT1_DUTY_CYCLE (0.500),
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.CLKOUT2_DIVIDE (4),
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.CLKOUT2_PHASE (0.000),
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.CLKOUT2_DUTY_CYCLE (0.500),
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.CLKOUT3_DIVIDE (4),
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.CLKOUT3_PHASE (270.000),
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.CLKOUT3_DUTY_CYCLE (0.500),
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.CLKOUT4_DIVIDE (32),
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.CLKOUT4_PHASE (180.000),
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.CLKOUT4_DUTY_CYCLE (0.500),
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.CLKOUT5_DIVIDE (16),
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.CLKOUT5_PHASE (0.000),
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.CLKOUT5_DUTY_CYCLE (0.500),
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.CLKIN_PERIOD (38.461),
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.REF_JITTER (0.001))
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pll_base_inst
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// Output clocks
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(.CLKFBOUT (clkfbout),
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.CLKOUT0 (clkout0),
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.CLKOUT1 (clkout1),
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.CLKOUT2 (clkout2),
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.CLKOUT3 (clkout3),
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.CLKOUT4 (clkout4),
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.CLKOUT5 (clkout5),
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// Status and control signals
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.LOCKED (LOCKED_OUT),
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.RST (1'b0),
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// Input clock control
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.CLKFBIN (clkfbout_buf),
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.CLKIN (clkin1));
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// Output buffering
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//-----------------------------------
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BUFG clkf_buf
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(.O (clkfbout_buf),
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.I (clkfbout));
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BUFG clkout1_buf
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(.O (wb_clk),
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.I (clkout0));
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BUFG clkout2_buf
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(.O (clk_fpga),
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.I (clkout1));
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BUFG clkout3_buf
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(.O (dsp_clk),
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.I (clkout2));
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BUFG clkout4_buf
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(.O (clk270_100),
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.I (clkout3));
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BUFG clkout5_buf
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(.O (clk_icap),
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.I (clkout4));
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BUFG clkout6_buf
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(.O (lms_clk),
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.I (clkout5));
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endmodule
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